JP3327601B2 - Test method for advanced control mechanism - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of testing a preceding control mechanism for verifying the function of a preceding control mechanism (for example, a pipeline control mechanism) in various information processing systems.

In recent years, the CPU of an information processing system has adopted an instruction execution pipeline control method in order to improve processing efficiency. In particular, recent MPUs employ a plurality of instruction execution pipeline control methods (called super scalar control) to further improve processing efficiency.

Therefore, there has been a demand for a test method capable of verifying the function of the preceding control mechanism with high accuracy.

[0004]

2. Description of the Related Art FIG. 12 shows a conventional example. In FIG. 12, 1 is an instruction generation unit, 2 is an instruction execution control unit, 3 is an execution result comparison unit, and 4 is an instruction area (memory area). Reference numeral 5 denotes an execution result area (memory area) for storing the execution result 1, and reference numeral 6 denotes an execution result area (memory area) for storing the execution result 2.

Conventionally, a test for verifying, for example, a pipeline control mechanism has been performed as a preceding control mechanism. When performing this test, as shown in FIG.
An instruction generation unit 1, an instruction execution control unit 2, an execution result comparison unit 3,
An instruction area 4, an execution result area 5, and an execution result area 6 are provided.

In order to increase the number of combinations of instructions, the instruction generation unit 1 generates an instruction sequence based on random numbers and stores the generated instruction sequence in the instruction area 4. afterwards,
The instruction execution control unit 2 changes the execution environment (preceding control mechanism, cache mechanism, and the like) for the generated instruction sequence in the instruction area 4 and executes the generated instruction sequence a plurality of times. 6 is stored.

In this case, the first execution result (execution result 1) is stored in the execution result area 5, and the second execution result (execution result 2) is stored in the execution result area 6. Thereafter, the execution result comparison unit 3 compares the execution results 1, execution results 2,... Stored in the execution result areas 5, 6, and obtains a test result of the preceding control mechanism.

[0008]

The above-mentioned conventional apparatus has the following problems. For example, even if there is a pipeline failure in a certain combination of specific instructions, there is a possibility that a plurality of execution results will be the same to execute the same instruction sequence.

For this reason, the ability to verify pipeline control faults was not sufficient. An object of the present invention is to solve such a conventional problem and improve the ability of a preceding control mechanism (such as a pipeline control mechanism) to verify a control failure.

[0010]

FIG. 1 is an explanatory view of the principle of the present invention, FIG. 1A is an explanatory view of a test method, and FIG. 1B is a view showing an instruction sequence in an instruction area.

In FIG. 1, the same components as those in FIG. 12 are denoted by the same reference numerals. Reference numeral 7 denotes an instruction sequence replacement processing unit, 8 denotes an instruction area (memory area), and 9 denotes an instruction area (memory area). The present invention is configured as follows in order to solve the above problems.

[0012] (1): the information processing system having a preceding control mechanism of instruction execution, the test program, generates an instruction sequence by a random number, a sequence of instructions to said generating by executing the above prior control mechanism, the Execution result (first run result)
And a method of testing the preceding control mechanism for the expected value, before
According to the test program, the instruction sequence is replaced within a range where the execution result does not change , and the execution result of the replaced instruction sequence is compared with the expected value.

(2): In the configuration (1), the test program allows the instruction sequence register to store the instruction sequence under the condition that the instruction destination register does not interfere with the source register of the subsequent instruction .
It was configured to be replaced . (3): In the configuration (1), according to the test program,
The instruction sequence is switched under the condition that the destination memory area of the instruction does not interfere with the source memory area of the subsequent instruction.

(4): In the configuration (1) , the test program
The ram is configured so that the instruction sequence is exchanged by exchanging instructions having different instruction types. (5): In the configuration (1) , according to the test program,
An instruction sequence is exchanged by grouping the same instruction types.

[0015]

The operation of the present invention based on the above configuration will be described with reference to FIG. When the test of the preceding control mechanism is performed, the processing is performed in the following order.

The instruction generator 1 generates an instruction sequence using random numbers in the instruction area 8 (memory area). The instruction execution control unit 2 executes the instruction sequence in the instruction area 8 and stores the result (execution result 1) in the execution result area 5 (memory area) as an expected value.

Next, the instruction sequence replacement processing unit 7 replaces the instruction sequence in the instruction area 8 and creates a new instruction sequence in the instruction area 9 (memory area). The instruction execution control unit 2 executes the instruction sequence in the instruction area 9 and stores the result (execution result 2) in the execution result area 6 (memory area).

The execution result comparison unit 3 takes in the execution result 1 (expected value) of the execution result area 5 and the execution result 2 of the execution result area 6 and compares them. That is,
It is confirmed that the execution result 1 (expected value) and the execution result 2 all match.

With the above arrangement, the operation of the preceding control mechanism can be changed and the operating conditions can be expanded, so that the verification accuracy of the preceding control mechanism (such as a pipeline) can be improved.

[0020]

Embodiments of the present invention will be described below with reference to the drawings. 2 to 11 are diagrams showing an embodiment of the present invention, in which the same components as those in FIGS. 1 and 12 are denoted by the same reference numerals.

Further, 11 is a test section, 12 is a test section, 1
3 is a test execution unit, 14 is a comparison unit, 15 is a work memory,
16 is a work register, 17 is an instruction fetch unit, 18 is an instruction decode unit, 19 is a pipeline control unit, 20-1
20-n are an instruction execution unit, 21 is an execution result reflection unit, 22
Denotes a register and memory access control unit, 23 denotes a register / file, and 24 denotes a memory.

Description of the system used in the test of this embodiment: see FIG. 2 FIG. 2 shows a system configuration diagram used in the test of this embodiment. FIG. 2 illustrates an example of a pipeline control mechanism (super scalar control mechanism) as the preceding control mechanism.

As shown, the system includes a test section 11 for executing a test, a test section 12 to be tested,
And a register and memory access control unit 22, a register / file 23, and a memory 24 connected to the unit under test 12.
Etc.

Description of Test Unit 11 The test unit 11 includes a test execution unit 13, a comparison unit 14, a work memory 15, a work register 16, and the like.

The test execution unit 13 executes various tests on the unit under test 12 by a test program, and the comparison unit 14 compares data after executing the instruction. The work memory 15 and the work register 16 are used when the test execution unit 13 performs a test.

The test execution unit 13 generates an instruction sequence using random numbers, stores the instruction sequence in the work memory 15, and then sends the instruction sequence to the unit under test 12 to execute a test. Also, the instruction sequence is replaced by the test execution unit 13 using the work memory 15, the work register 16, and the like.
2 to perform the test.

The test execution unit 13 receives the execution result of the instruction sequence in the unit under test 12 and performs a comparison process. Note that the test execution unit 13 corresponds to the combined function of the instruction generation unit 1, the instruction execution control unit 2, the instruction sequence replacement processing unit 7, and the like in FIG. Further, the comparison unit 14 corresponds to the execution result comparison unit 3 in FIG.

Description of the Unit under Test 12 and the Like The unit under test 12 includes an instruction fetching unit 17 and an instruction decoding unit 18, as well as a pipeline control unit 19, instruction execution units 20-1 to 20 -n, and an execution unit. A pipeline control mechanism including a result reflection unit 21 and the like is provided.

A register and memory access control unit 22 is connected to the unit under test 12 for performing pipeline control, and the register and memory access control unit 22 includes a register / file 23, The memory 24 is connected.

In the above-mentioned pipeline control mechanism, for example, the instruction execution unit 20-1 is an instruction execution unit for a fixed-point number, and the instruction execution unit 20-2 is an instruction execution unit for a floating-point number and an instruction execution unit 20. -N is an execution unit for instructions such as memory load / store.

Description of Test Method When a test is performed, the test section 11 generates an instruction sequence based on random numbers for the test section 12 of the information processing system, and causes the test section 12 to execute the generated instruction sequence. Then, the execution result (first running result) is set as an expected value.

Thereafter, the test unit 11 performs the above-described instruction sequence exchange processing within a range where the execution result does not change, causes the unit under test 12 to execute the exchanged instruction sequence again, and compares the execution result with the comparing unit 14. Compare with the above expected value.

An embodiment of the instruction replacement process by the test unit 11 will be described below. The registers (r1 to r6), files (f1 to f6), and memory areas (AREA1, AREA2) described in the following embodiments are a part of the register / file 23 and the memory 24 in FIG. W1 and C1 are areas of the work memory 15.

(Explanation of First Embodiment) FIGS. 3 and 4 are diagrams showing a first embodiment of the instruction replacement process. FIG. 3 is an explanatory diagram of the instruction sequence, and FIG. 6 is a flowchart of the instruction replacement process. is there.

In the first embodiment, instructions are exchanged by avoiding register interference. This test method can be applied to a CPU having one pipeline and a CPU having a plurality of pipelines (see FIG. 2).

Description of Instruction Swapping Logic In this example, a destination register of a certain instruction swaps an instruction sequence under a condition that does not interfere with a source register of a subsequent instruction.

For example, a destination register of a fixed-point instruction replaces an instruction sequence under a condition that does not interfere with a source register of a subsequent instruction. : Explanation of instruction sequence ... see FIG. 3 When performing the above test, the test execution unit 13 generates an instruction sequence using random numbers, stores the generated instruction sequence in the instruction area 1, and follows the instruction replacement logic. , Instructions, and the resulting instruction sequence is stored in the instruction area 2.

As shown, the instruction sequence in the instruction area 1 is
“DIV: divide-by-zero exception interrupt”, “ADD: r1 +
r2 → r3 ”,“ SUB: r1-r2 → r5 ”,“ O
R: r3 / r5 → r4 ”,“ XXX: privileged instruction exception interrupt ”,...

Then, among the instructions in the instruction area 1, "A
DD ”and“ SUB ”are exchanged and stored in the instruction area 2. Even if these two instructions are exchanged, there is no register interference, so that the result is not affected.

Description of Instruction Swapping Process--See FIG. 4 FIG. 4 shows a flowchart of the instruction swapping process of the first embodiment. Note that S1 to S7 indicate processing numbers.

In this processing, the processing is performed for each instruction sequence shown in FIG. 3, but the processing for exchanging the instruction sequences is performed for the instructions between the interrupted instructions. That is, in the example of FIG. 3, an instruction between “DIV” and “XXX” is a replacement target.

S1: Pointer (address pointer) P1
Is set to the start address of the replacement instruction. In the example of FIG. 3, “D” in the instruction sequence stored in the instruction area 1
Since the “IV: divide-by-zero exception” instruction generates an interrupt, the next instruction is “ADD: r1 + r2 → r
3 "instruction.

Therefore, the pointer P1 has "AD
Set the start address of the "D" instruction. S2: The start address of the instruction following the pointer P1 is set in the pointer (address pointer) P2.

In this case, for the first time, "S
UB: r1-r2 → r5 "Sets the start address of the instruction. S3: Determine whether the destination register of the instruction of the pointer P1 matches the source register of the instruction of the pointer P2.

In this case, at the first time, the destination register of the instruction of the pointer P1 is r3, and the source registers of the instruction of the pointer P2 are r1 and r2. Therefore, in the first determination, they do not match.

S4: If the two do not match in the process of S3, it is determined whether or not the destination register of the instruction of the pointer P2 matches the source register of the instruction of the pointer P1.

In this case, for the first time, the destination register of the instruction of the pointer P2 is r5, and the source registers of the instruction of the pointer P1 are r1 and r2. Therefore, in the first determination, they do not match.

S5: If the two do not match in the process of S4, the instruction of the pointer P1 and the instruction of the pointer P2 are exchanged because there is no interference between the registers. S6: If the two match in the processing of S3 and S4,
When the processing of S5 is completed, the pointer P1
Is set to the start address of the instruction following the pointer P2.

S7: Subsequently, if it is out of the range of the instruction replacement, the processing is terminated. If not, the processing is repeated from the processing of S2. The replacement range in this case is from “ADD” to “OR”.

The processing from S2 to S6 performed from the second time is as follows. That is, in the process of S3,
The destination register of the instruction of the pointer P1 is
The register r5, and the source registers of the instruction of the pointer P2 are the registers r3 and r5.

Therefore, in the second judgment, since they match, they are not subject to instruction replacement. By the above processing, in the example of FIG. 3, the “ADD” and “SUB” instructions are exchanged.

(Explanation of Second Embodiment) FIGS. 5 and 6 show a second embodiment of the present invention. FIG. 5 is an explanatory diagram of an instruction sequence, and FIG. 6 is a flowchart of instruction replacement processing. .

In the second embodiment, instructions are replaced by avoiding operand memory interference.
This test method consists of a CPU with one pipeline and
The present invention can be applied to a CPU having a plurality of pipelines (see FIG. 2).

Description of Instruction Interchange Logic In this example, the instruction sequence is exchanged under the condition that the destination memory area of a certain instruction does not interfere with the source memory area of the subsequent instruction.

For example, the instruction sequence is exchanged under the condition that the storage in the memory and the retrieval from the memory do not interfere with each other. : Explanation of instruction sequence ... see FIG. 5 When performing the above test, the test execution unit 13 generates an instruction sequence using random numbers, stores the generated instruction sequence in the instruction area 1, and follows the instruction replacement logic. , Instructions, and the resulting instruction sequence is stored in the instruction area 2.

As shown, the instruction sequence in the instruction area 1 is:
“DIV: divide-by-zero exception interrupt”, “ST: r1 → A”
REA1, "LD: AREA2 → r4", "SUB:
r1-r2 → r5 "," XXX: privileged instruction exception interrupt ",...

Then, among the instructions in the instruction area 1, "S
The instructions “T” and “LD” are exchanged and stored in the instruction area 2. Note that even if these two instructions are exchanged, there is no interference with the operand memory, so that the result is not affected.

Description of Instruction Interchange Processing—See FIG. 6 FIG. 6 shows a processing flowchart of the second embodiment. In addition,
S11 to S17 indicate processing numbers.

In this processing, the processing is performed for each instruction sequence in FIG. 5, but the instruction exchange processing is performed for the instructions between the interrupted instructions. That is, FIG.
In the example, the instruction between "DIV" and "XXX" is a replacement target.

S11: The start address of the replacement instruction is set in the pointer P1. In the example of FIG. 5, since the “DIV: division-by-zero exception interrupt” instruction in the instruction sequence of the instruction area 1 generates an interrupt, the next instruction is “ST: r
1 → AREA1 ”.

Therefore, the pointer P1 has "ST:
Set the start address of the “r1 → AREA1” instruction. S12: The start address of the instruction following the pointer P1 is set in the pointer P2.

In this case, the first time, the pointer P2
The start address of the “LD: AREA2 → r4” instruction is set. S13: It is determined whether or not the destination memory of the instruction of the pointer P1 matches the source memory of the instruction of the pointer P2.

In this case, for the first time, the destination memory of the instruction of the pointer P1 is AREA1, and the source memory of the instruction of the pointer P2 is AREA2.
Therefore, in the first determination, they do not match.

S14: If the two do not match in the process of S13, it is determined whether or not the destination register of the instruction of the pointer P2 matches the source register of the instruction of the pointer P1.

In this case, at the first time, the destination register of the instruction of the pointer P2 is r4, and the source register of the instruction of the pointer P1 is r1. Therefore,
In the first determination, they do not match.

S15: If the two do not match in the process of S14, the instruction of the pointer P1 and the instruction of the pointer P2 are replaced because there is no interference between the registers. S16: If the two match in the processes of S13 and S14, and if the process of S15 ends, the start address of the instruction following the pointer P2 is set in the pointer P1.

S17: Subsequently, if it is out of the range of the instruction replacement, the process is terminated. If not, the process is repeated from the process of S12. The replacement range in this case is from “ST” to “SUB”.

The processing from S12 to S16 performed from the second time is as follows. That is, in the process of S13, since both are registers, there is no memory match,
In the process of S14, since the memory and the register are compared, there is no match between the registers.

Therefore, in the second judgment, there is no instruction replacement target. By the above processing, in the example of FIG. 5, the “ST” and “LD” instructions are exchanged.

(Explanation of Third Embodiment) FIGS. 7 and 8 show a third embodiment of the present invention. FIG. 7 is an explanatory diagram of an instruction sequence, and FIG. 8 is a flowchart of instruction replacement processing. .

The third embodiment is an example in which instructions of different instruction types are exchanged. This test method uses a CPU with multiple pipelines based on superscalar control, etc.
(See FIG. 2).

That is, this is a method of exchanging instructions executed in another pipeline. In this case, the instruction type means an instruction type such as a “fixed-point operation instruction” or a “floating-point operation instruction”.

Description of Instruction Swapping Logic In this example, depending on the type of instruction, the executed pipeline swaps instructions under conditions that do not cause interference. For example, the following fixed-point instruction is replaced with a floating-point instruction.

Description of Instruction Sequence—See FIG. 7 When performing the above test, the test execution unit 13 generates an instruction sequence by using random numbers, stores the generated instruction sequence in the instruction area 1, The instructions are exchanged according to the exchange logic, and the resulting instruction sequence is stored in the instruction area 2.

As shown, the instruction sequence in the instruction area 1 is
“DIV: divide-by-zero exception interrupt”, “ADD: r1 +
r2 → r3 ”,“ FMUL: f1 * f2 → f5 ”,“ O
R: r3 / r5 → r4 ”,“ XXX: privileged instruction exception interrupt ”,...

Of the instructions in the instruction area 1, the fixed-point instruction “ADD” and the floating-point instruction “FMUL” are exchanged and stored in the instruction area 2. : Explanation of the instruction replacement process ... see FIG. 8 FIG. 8 shows a processing flowchart of the third embodiment. In addition,
S21 to S26 indicate processing numbers.

In this processing, processing is performed for each instruction sequence in FIG. 7, but instruction replacement processing is performed for instructions between instructions in which an interrupt has occurred. That is, FIG.
In the example, the instruction between "DIV" and "XXX" is a replacement target.

S21: The start address of the replacement instruction is set in the pointer P1. In the example of FIG. 7, since the "DIV: divide-by-zero exception interrupt" instruction of the instruction sequence in the instruction area 1 generates an interrupt,
The next instruction is “ADD: r1 + r2 → r3”.

Therefore, the pointer P1 has "AD
D: r1 + r2 → r3 ”The start address of the instruction is set. S22: The start address of the instruction following the pointer P1 is set in the pointer P2.

In this case, the first time, the pointer P2
The start address of the instruction “FMUL: f1 * f2 → f5” is set. S23: The type of the instruction of the pointer P1 is the pointer P2
To determine if it matches the instruction type.

In this case, for the first time, the instruction type of the pointer P1 is the fixed-point instruction “ADD”, and the instruction type of the pointer P2 is the floating-point instruction “FMUL”.
It is. Therefore, in the first determination, the two types do not match.

S24: If the two do not match in the process of S23, the instruction of the pointer P1 and the pointer P
Swap with instruction 2. S25: If the two match in the process of S23, and if the process of S24 ends, the pointer P1
Is set to the start address of the instruction following the pointer P2.

S26: Subsequently, if the instruction replacement range is exceeded, the processing is terminated. If not, the processing from S22 is repeated. The replacement range in this case is from “ADD” to “OR”.

By the above processing, in the example of FIG. 7, the fixed-point instruction "ADD" and the floating-point instruction "FMUL"
The instructions will be swapped. (Explanation of Fourth Embodiment) FIGS. 9, 10, and 11 are diagrams showing a fourth embodiment of the present invention. FIG. 9 is an explanatory diagram of an instruction sequence, and FIGS. It is a flowchart (the 1 and the 2).

The fourth embodiment is an example in which the same instruction types are collected and instructions are exchanged. This test method is based on C with multiple pipelines by super scalar control, etc.
Applicable to PU (see FIG. 2).

Description of Instruction Interchange Logic In this example, instructions executed in the same pipeline are grouped and exchanged for each type of instruction. For example, the following fixed-point instructions and floating-point instructions are collected and exchanged.

That is, in the case of a CPU in which the fixed-point instruction and the floating-point instruction are executed in different pipelines, the fixed-point instruction group and the floating-point instruction group are gathered and exchanged, respectively.

Description of Instruction Sequence—See FIG. 9 When performing the above test, the test execution unit 13 generates an instruction sequence by using random numbers, stores the generated instruction sequence in the instruction area 1, The instructions are exchanged according to the exchange logic, and the resulting instruction sequence is stored in the instruction area 2.

As shown, the instruction sequence in the instruction area 1 is
“DIV: divide-by-zero exception interrupt”, “ADD: r1 +
r2 → r3 ”,“ FMUL: f1 * f2 → f5 ”,“ O
R: r3 / r5 → r4 ”,“ SUB: r1-r2 → r
3 "," FADD: f2 * f3 → f6 "," AND: r
1 & r2 → r6 ”,“ XXX: Privileged instruction exception interrupt ”
...

Then, in the instruction sequence of the instruction area 1, the fixed-point instructions "ADD", "OR", "SUB",
An instruction group of “AND” is aggregated, and an instruction group of “FMUL” and “FADD” of floating-point instructions are aggregated and exchanged.

Description of Instruction Interchange Processing--FIG.
0 and FIG. 11 FIGS. 10 and 11 show processing flowcharts of the fourth embodiment. In addition, S31 to S41 indicate a processing number.

In this processing, the processing is performed on the instruction sequence in the instruction area 1 in FIG. 9, but the instruction replacement processing is performed on the instructions between the interrupted instructions. That is, in the example of FIG. 9, an instruction between “DIV” and “XXX” is a replacement target.

Note that W1 and C1 used in the following processing are used.
Is an area in the work memory 15 (see FIG. 2). F1 to f6 are areas of the file (in the register / file 23 in FIG. 2).

S31: The start address of the replacement instruction is set in the pointer P1. Also, the start address of the work area is set in W1, and the counter C1 is cleared to zero. In the example of FIG. 9, among the instruction strings stored in the instruction area 1, "DI
Since the "V: divide-by-zero exception interrupt" instruction generates an interrupt, the next instruction is "ADD".

Therefore, the pointer P1 has "AD
Set the start address of the "D" instruction. S32: Insert the instruction of the pointer P1 into the area of W1.
Further, the address of the next work area is set in the area of W1, and the value of C1 is counted up (+1).

S33: The start address of the instruction following the pointer P1 is set in the pointer P2. S34: The type of the instruction of pointer P1 is pointer P2
To determine if it matches the instruction type.

S35: If the two match in the process of S34, the instruction of the pointer P2 is inserted into the area of W1. Further, the address of the next work area is set in W1, and C1 is counted up (+1). Further, a processed mark is attached to the instruction of the pointer P2.

S36: If the two do not match in the process of S34, and if the process of S35 is completed, the start address of the instruction following the pointer P2 is set to the pointer P2 (P2). Add one address).

S37: Subsequently, if it does not exceed the range of instruction replacement, the process returns to S34 to perform the processing. If it exceeds the range of instruction replacement, the next processing (S
38) is performed.

S38: The start address of the instruction following the pointer P1 is set in the pointer P1. S39: Perform the process of S38 to determine whether or not the range of instruction replacement has been exceeded.

S40: If it is determined in step S39 that the instruction does not exceed the instruction replacement range, it is determined whether the instruction of the pointer P1 is a processed mark. As a result, if the processed mark is attached, the process returns to S38 to perform the processing.

However, if the mark is not a processed mark,
Returning to S32, the process is performed. S41: If the processing in S39 is beyond the range of the instruction replacement, the instruction sequence in the work area is written back to the instruction replacement area, and the processing is terminated.

By the above processing, the fixed-point instructions “ADD”, “OR”, “S”
The instruction groups of “UB” and “AND” are aggregated, and the instruction groups of “FMUL” and “FADD” of floating-point instructions are aggregated and exchanged.

(Other Embodiments) Although the embodiments have been described above, the present invention can be implemented as follows. The instruction sequence is not limited to the instruction sequence described in the above embodiment, but can be executed by various instruction sequences.

The present invention can be applied to verification of a preceding control mechanism other than the pipeline control mechanism in the same manner as in the above embodiment.

[0106]

As described above, the present invention has the following effects. : By changing the instruction sequence, the pipeline operation can be changed, and the verification accuracy can be improved.

In particular, in the multi-pipeline system based on superscalar control, the order of input of instructions to each pipeline changes, so that the operating conditions of the pipeline mechanism can be expanded. As a result, verification accuracy can be improved.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a system configuration diagram of an embodiment of the present invention.

FIG. 3 is an explanatory diagram of an instruction sequence according to the first embodiment.

FIG. 4 is a flowchart of an instruction replacement process according to the first embodiment.

FIG. 5 is an explanatory diagram of an instruction sequence according to a second embodiment.

FIG. 6 is a flowchart of an instruction replacement process according to the second embodiment.

FIG. 7 is an explanatory diagram of an instruction sequence according to a third embodiment.

FIG. 8 is a flowchart of an instruction replacement process according to the third embodiment.

FIG. 9 is an explanatory diagram of an instruction sequence according to a fourth embodiment.

FIG. 10 is a flowchart (part 1) of an instruction replacement process according to the fourth embodiment.

FIG. 11 is a flowchart (part 2) of an instruction replacement process according to the fourth embodiment.

FIG. 12 is an explanatory diagram of a conventional technique.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Instruction generation part 2 Instruction execution control part 3 Execution result comparison part 5, 6 Execution result area (memory area) 7 Instruction sequence exchange processing part 8, 9 Instruction area (memory area)

────────────────────────────────────────────────── ─── Continued on the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) G06F 11/22-11/26 G06F 9/38 JICST file (JOIS)

Claims (5)

(57) [Claims] 1. An information processing system having an advance control mechanism for instruction execution, a test program generates an instruction sequence using random numbers, causes the preceding control mechanism to execute the generated instruction sequence, and executes the execution result. (The first run result)
In the test method of the preceding control mechanism having an expected value, the instruction sequence is replaced by the test program as long as the execution result does not change, and the execution result of the replaced instruction sequence is compared with the expected value. Testing method for advanced control mechanism. 2. The test method for a preceding control mechanism according to claim 1, wherein the test program replaces the instruction sequence under a condition that a destination register of the instruction does not interfere with a source register of a subsequent instruction. . 3. The pre-control mechanism according to claim 1, wherein the test program replaces the instruction sequence under a condition that the destination memory area of the instruction does not interfere with the source memory area of the subsequent instruction. Test method. 4. The test method for a preceding control mechanism according to claim 1, wherein the instruction sequence is exchanged by exchanging instructions having different instruction types according to the test program. 5. The test method for a preceding control mechanism according to claim 1, wherein the instruction sequence is exchanged by assembling the same instruction types by the test program.