WO2020113526A1

WO2020113526A1 - Chip verification method and device

Info

Publication number: WO2020113526A1
Application number: PCT/CN2018/119613
Authority: WO
Inventors: 杨鸿志
Original assignee: 华为技术有限公司
Priority date: 2018-12-06
Filing date: 2018-12-06
Publication date: 2020-06-11
Also published as: CN113168364A

Abstract

The present application provides a chip verification method and device, for use in solving the problems in the prior art that personnel need to participate when verifying whether a bug exists in a chip, operation is complex, and verification efficiency is low. The method comprises: method I, selecting a corresponding instruction sequence on the basis of a determined random numerical value, and then repeatedly executing steps that satisfy a condition; method II, after determining a control parameter, and after generating an actual instruction example according to the instruction sequence selected on the basis of an unused random numerical value and the determined control parameter, repeatedly executing the steps that satisfy the condition. Therefore, in a chip verification process, it is not necessary for personnel to participate, the operation is simple, and the verification efficiency can be improved.

Description

Chip verification method and device

Technical field

This application relates to the field of electronic technology, in particular to a chip verification method and device.

Background technique

With the development of large-scale integrated circuits and multi-threaded multi-core processors, there is an increasing demand for verifying whether the chip has problems, such as verifying the central processing unit (CPU) on the system on chip (SOC) The consistency of the cache of other devices and the cache of other devices in the SOC is one aspect to verify whether there is a problem with the chip.

In the prior art, a "constraint-based random test template" method is generally used to verify whether there is a problem with the chip. This method first defines a test template. The test template includes an instruction set and instruction constraints, and then randomizes the instruction set according to the instruction constraints. The generated instruction combination forms an instruction sequence, and an instruction use case is generated based on the instruction sequence and the default control parameters. The control parameters are parameters used to control different instructions in the instruction sequence when they are run. Therefore, the different function values of the function points of the chip to be verified are output after the instruction case of the chip to be verified is run, and the test coverage is obtained according to the ratio of the number of output function values and the number of function values expected to be obtained, and the verification personnel analyzes Test coverage. If the test coverage is not as expected, modify the instruction set in the test template according to the analysis results. For example, increase the instruction set in the instruction set to test the function corresponding to the function value that is not output, thereby improving the test coverage. ，Through the operation instruction use case of the chip to be verified once, until the test coverage reaches the expected, and there are no defects in the process of running the instruction use case, it proves that the chip to be verified is no problem; If the test coverage is in the process of running the instruction use case When the rate reaches the expected level and a bug occurs, the verification stops, and the technician repairs the defect of the chip to be verified according to the bug.

When the "constraint-based random test template" verification method is used to verify whether there is a problem with the chip, due to the need for verification personnel to participate, the operation is cumbersome and the verification efficiency is low.

Summary of the invention

The embodiments of the present application provide a chip verification method and device, which are used to solve the problems of verifying whether there is a problem with the chip in the prior art, requiring verification personnel to participate, more cumbersome operations, and lower verification efficiency.

In the first aspect, the present application provides a chip verification method, which includes determining a random value; selecting a corresponding instruction sequence in a test template based on the random value, the test template including multiple instructions; repeating execution based on the instruction sequence The following steps:

Traverse a control parameter in the preset control parameter set that has not been traversed, and generate an actual test command use case according to the selected instruction sequence and the control parameter obtained by traversing;

When the test coverage obtained when the first chip runs the actual test instruction use case is greater than a preset value, the first chip is controlled to run the actual test instruction use case multiple times, and if there is a defect bug, it ends, otherwise the traversal is performed again A step of a control parameter in the preset control parameter set that has not been traversed.

In the above method, after the verification device or component used to verify the chip determines a random value, an instruction series is generated based on the random value, and the instruction sequence and the traversed different control parameters are respectively formed into different actual test instruction use cases, and then Different actual test command use cases generated based on different control parameters and the same instruction sequence can be used to verify the verification chip (ie, the first chip), and when the first chip runs an actual test command use case to obtain a test coverage greater than a preset value Then, the first chip can be further controlled to continue to run the actual instruction test instruction use case multiple times until a bug is detected in the chip to be verified. Therefore, the verification efficiency of the chip can be improved, and no personnel is required in the whole process, and the verification efficiency and accuracy can be improved.

In a possible design, when a random value is determined, a random value may be randomly generated first; based on the random value, a corresponding instruction sequence is selected in the test template, and generated according to the selected instruction sequence and default control parameters A simulation test instruction use case; when the test coverage obtained when the first chip runs the simulation test instruction use case is greater than a preset value, the generated random value is used as a random value determined above.

Since the test coverage obtained after the first chip runs the instruction sequence composed of the instruction sequence obtained based on the random value and the default control parameters is greater than the preset value, it can be determined that the random value is a better random value, and the better The random number is used as the random number used in the subsequent generation of actual test instruction use cases, which can further improve the test accuracy.

In a possible design, the selecting a corresponding instruction in the test template based on the random value to obtain an instruction sequence includes: calculating a plurality of instruction index values based on the random value, and based on the calculated plurality of instructions The index value selects the corresponding instruction sequence in the test template.

In the above method, how to obtain the instruction sequence based on the random value is given. Since the instruction index value calculated based on the random value is used to select the corresponding instruction sequence, the method for selecting the instruction is simpler and easier to operate.

In a possible design, if the control parameters that are not traversed are not traversed in the control parameter set, the execution may return to determine other random values, and then continue to determine the instruction sequence based on the determined other random values, based on other random The command sequence determined by the value is combined with different control parameters to generate different actual test command use cases, and the first chip continues to be tested until the bug is tested.

In the above method, in the process of chip verification, if the control parameters cannot be traversed, it returns to the step of determining other random values, so as to enter the next new test cycle, so that the verification process can automatically cycle.

In a possible design, after obtaining the test coverage obtained when the first chip runs the simulation test instruction use case is greater than a preset value, continue to control the first chip to run the simulation test instruction use case M M test coverages are obtained respectively; when it is determined that at least N test coverages among the M test coverages are greater than a preset value, the random value generated is determined as a determined random value. Both M and N are positive integers, and M>=N.

This can ensure that the determined random value is more optimized, and provide a good basis for subsequent generation of actual test instruction use cases with better test results.

In a possible design, if a bug occurs on the first chip during the test, the determined random value may also be stored in a random number set, which may be used to provide randomness when verifying the second chip Value.

In this way, due to a bug in the verification chip, it proves that the selected random value is more optimized. Therefore, storing the selected random value in the random number set can continuously learn and accumulate better random values in the random number set, so as to verify other A chip (such as a second chip) may preferentially provide an excellent random value, so as to reduce the time for searching and determining a random value when verifying the second chip, and further improve the verification efficiency.

In a possible design, the default control parameter may be a control parameter in the preset control parameter set, or may not be a control parameter in the preset control parameter set, and may be selected according to needs Default control parameters.

In a possible design, the test coverage may be determined by at least one of the following ways:

Use the read system status register to general register MRS instruction to read the performance monitoring unit PMU register to obtain the test coverage, as the test coverage of the first chip to run the actual test instruction use case; or

Use the MRS instruction to read the special register to obtain the test coverage, as the test coverage of the first chip running the actual test instruction use case; or

A load instruction is used to read the memory of the first chip to obtain a test coverage, which is used as the test coverage of the first chip to run the actual test instruction use case.

In the second aspect, the present application provides another chip verification method, including determining a control parameter; selecting a corresponding instruction sequence in a test template based on an unused random value, the test template including multiple instructions; according to the selection The instruction sequence and the control parameters to generate an actual test instruction use case; when the test coverage obtained when the first chip runs the actual test instruction use case is greater than a preset value, the first chip is controlled to run the actual test The instruction use case is repeated many times, and it ends if there is a bug, otherwise, the step of selecting the corresponding instruction sequence based on other unused random values is executed again.

In the above method, after a verification device or component for verifying a chip determines a control parameter, a combination of command series generated based on the control parameter and different random values is used to obtain different actual test command use cases, which can be used based on the same control parameter And different actual test command use cases generated with different random values to verify the verification chip (ie, the first chip), and when the test coverage obtained by running an actual test command use case on the first chip is greater than the preset value, the control of the first A chip continues to run the actual command test command use case multiple times until a bug in the chip to be verified is tested. Therefore, it is possible to perform cyclic verification during chip verification without personnel involvement, thereby improving verification efficiency and verification accuracy.

In a possible design, when a control parameter is determined, a control parameter may be randomly selected; a corresponding instruction sequence is selected in a test template using a corresponding random value, and a simulation test instruction is generated based on the instruction sequence and the control parameter Use case; when the test coverage obtained when the first chip runs the simulation test instruction use case is greater than a preset value, the selected control parameter is used as a control parameter determined above.

Since the test coverage obtained after the first chip runs the instruction sequence obtained based on the corresponding random value and the instruction use case generated by the control parameter is greater than the preset value, it can be determined that the control parameter is a better control parameter, and the better The random value of is used as the control parameter for the subsequent generation of actual test instruction use cases, which can further improve the test accuracy.

In a possible design, the selecting a corresponding instruction sequence in the test template based on an unused random value includes: calculating a plurality of instruction index values based on an unused random value, and based on the calculated The multiple instruction index values select corresponding instruction sequences in the test template.

In a possible design, after obtaining the test coverage obtained when the first chip runs the simulation test instruction use case is greater than a preset value, continue to control the first chip to run the simulation test instruction use case M At each time, M test coverages obtained separately; when it is determined that at least N test coverages among the M test coverages are greater than a preset value, then determine the selected control parameter as a determined control parameter, Wherein M and N are both positive integers, and M>=N.

This can ensure that the determined control parameters are more excellent, and provide a good basis for subsequent generation of actual test command use cases with better test results.

In a possible design, if a bug occurs on the first chip during the test, the determined control parameter may also be stored in a control parameter set, which may be used to provide control when verifying the second chip parameter.

In this way, because the verification chip has a bug, it proves that the selected control parameters are more optimized. Therefore, storing the determined control parameters in the control parameter set can enable the continuous learning and accumulation of better control parameters in the control parameter set, so as to verify other chips. (For example, the second chip), priority can be given to providing better control parameters, so as to reduce the time for searching and determining control parameters when verifying the second chip, and further improve the verification efficiency.

In a third aspect, the present application further provides an apparatus having the functions related to the above-mentioned first aspect or second aspect. The function can be realized by hardware, or can also be realized by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above functions.

In a possible design, the structure of the device may include a processing unit and a storage unit, and may also include a communication unit, etc. These units may perform the corresponding in the first aspect or the second aspect example. For example, the structure of the device may include a processor and a memory, the processor and the memory are coupled, and the memory stores necessary program instructions and data. The memory is used to store a computer program; the processor is configured to execute the computer program stored in the memory to complete the corresponding function in the first aspect or the second aspect described above.

According to a fourth aspect, the present application also provides a computer storage medium that stores computer-executable instructions, which when used by the computer are used to cause the computer to execute the above-mentioned first The method mentioned in any possible design in one aspect, or performing the method mentioned in any possible design in the second aspect above.

In a fifth aspect, the present application also provides a computer program product containing instructions that, when run on a device, cause the device to perform the method mentioned in any of the possible designs in the first aspect above, or cause The device performs the method mentioned in any possible design of the second aspect above.

According to a sixth aspect, the present application further provides an apparatus, which may be a chip connected to a memory, and used to read and execute program instructions stored in the memory to implement any of the first aspect A method mentioned in a possible design, or a method mentioned in any possible design of the second aspect above.

BRIEF DESCRIPTION

FIG. 1 is a schematic diagram of an existing verification framework for verifying chips;

2 is a schematic diagram of a verification framework for verifying a chip provided by an embodiment of the present application;

FIG. 3 is a specific flowchart of a method for verifying a chip provided by an embodiment of the present application;

4 is a schematic diagram of a process of selecting a corresponding instruction sequence according to a random value provided by an embodiment of the present application;

5 is a flowchart of a complete method for chip verification provided by an embodiment of the present application;

6 is a specific flowchart of another method for verifying a chip provided by an embodiment of the present application;

7 is a flowchart of another complete method of chip verification provided by an embodiment of the present application;

8 is a schematic structural diagram of a first device provided by an embodiment of this application;

9 is a schematic structural diagram of a second device provided by an embodiment of the present application.

detailed description

The embodiments of the present application will be further described in detail below with reference to the drawings.

The embodiments of the present application provide a chip verification method and device, to solve the problems that the verification chip in the prior art has bugs, requires personnel participation, is cumbersome to operate, and has low verification efficiency. Among them, the method and the device are based on the same inventive concept. Since the principles of the method and the device to solve the problem are similar, the implementation of the device and the method can be referred to each other, and the repetition is not repeated here.

When developing a new chip, the R&D personnel need to verify the various functions of the chip. Only after the verification is successful can the chip be put on the market. When verifying the function of the chip, one of the most critical issues is to verify whether there is a bug in the chip. If there is a bug, the verification personnel needs to analyze the bug, find out the cause of the bug, and continue to work on the chip after solving the cause of the bug. verification. Among them, the verification of the chip can be the verification of the "memory consistency" of the chip, the interruption of the CPU, the exception, the page table and virtualization, branch prediction, instruction fetching, decoding, decomposition of micro-operations, distribution, transmission, write back, instructions Whether there are bugs in submission and rollback can also be used to verify all SOC systems including CPU.

Before introducing the embodiments of the present application, first, several key concepts involved in the embodiments of the present application are defined and described, so as to better understand the implementation process of the embodiments of the present application.

1) Random number, which is a value randomly generated by some random algorithm, can be a 64-bit hexadecimal number, based on the hexadecimal number can use a preset algorithm to calculate a set of digital sequence, the digital sequence It can be used as a sequence of instruction index values; a random algorithm refers to the use of a random function, and the return value of the random function directly or indirectly affects the execution flow or execution result of the algorithm.

2). Test template refers to a test instruction library generated in advance by testers based on experience, used to store instruction sets and instruction constraints. The instruction set contains at least one instruction, which includes various kinds of pre-programmed by testers for different chips. Different instructions, different instructions can constitute an instruction sequence, and an instruction sequence can be combined with different control parameters used to test the chip to be tested to form a test instruction use case; the instruction constraints include constraints for selecting instructions, that is, calculation instructions Index value function.

3). Control parameters, used to control the parameters used by different instructions in the instruction sequence during operation. In order to be able to test different test points of different chips to be verified, different test parameters can be set for the chips to be verified to achieve different The purpose of the test points are tested.

4). Test instruction use cases are generated operating programs that can directly affect the chip to be verified. Usually, when the chip to be verified runs the running program, if there is a problem, a bug is usually triggered. The test instruction use case is composed of an instruction sequence and control parameters. The process of running the instruction use case of the chip to be verified is to use the instructions in the instruction use case to access the corresponding address in the chip to be verified to obtain the corresponding data in the chip. Control parameter indication.

5). Test coverage refers to the ratio of the number of tested different function values output by the chip to be verified after running the test instruction use case and the number of expected function values.

6). The instruction index value is an index value calculated by using a preset algorithm according to a random value. Based on different instruction index values, corresponding instructions can be indexed in the test template.

7) Multiple means two or more.

8) In the description of this application, the words "first" and "second" are only used to distinguish the description, and cannot be understood as indicating or implying relative importance, or as indicating or implying the order.

At present, for chip verification, verification processing is usually performed based on the verification framework shown in FIG. 1. As shown in FIG. 1, the schematic diagram of the existing verification framework includes a random instruction generator, and the random instruction generator includes a random value generator and a test template. And instruction generation module. Among them, the test template includes an instruction set and instruction constraints. The instruction set is pre-defined. The instruction set contains multiple instructions; instruction constraints store some constraints for generating instruction index values; the instruction generation module is used for The instruction index value generated according to the instruction constraint indexes the instruction from the instruction set, and finally obtains the instruction sequence. When verifying whether there is a problem with a chip to be verified, the random number generator is used to randomly generate a random value. The random value here can also be called a "seed", which can be a 64-bit hexadecimal Numerical value, the random number generator will generate multiple instruction index values according to the "seed" and the constraint conditions in the instruction constraints, and then the instruction generation module selects corresponding multiple instructions from the instruction set according to the multiple instruction index values to form an instruction sequence , The instruction sequence and the default control parameters are combined into an instruction use case, and output to the target chip (that is, the chip to be verified), the instruction use case is run by the chip to be verified, and then with the help of eda (electronic design automation) "Assert" or "test coverage" and other functions to collect the test coverage of the target chip when running the instruction use case, and then the "coverage analysis tool" will store the collected test coverage and other information into a folder. Subsequent verification personnel can modify or improve the instruction set in the test template according to the test coverage and other information stored in the file; during the process of verifying the instruction use case of the target chip, if there is a bug, the verification is stopped, and the verification personnel can bug analysis.

It should be noted that the assertion refers to the inspection of the non-conformance when running the instruction use case. When the non-conformity occurs, an assertion will occur, that is, an error will be reported, and the verification will stop.

In order to facilitate understanding of the method for verifying the chip in the prior art, the following is an example.

For example, there are 10 instructions in the instruction set in the test template, instruction A, instruction B, instruction C, instruction D, instruction E, instruction F, instruction G, instruction H, instruction I, instruction J, the random number generator is randomly selected A "seed" is 123. According to the instruction constraint conditions in the instruction constraint and "seed" 123, the randomly selected instruction sequence in the test template is instruction A, instruction E, instruction F, and then instruction A, instruction E, instruction F and the default control parameters are combined into a test command use case and output to the target chip. After the target chip runs the test command sequence, the test coverage obtained by the target chip running the test command use case is collected by the eda tool. If the collected test coverage information is 70%, if the target chip needs to verify 10 functions, 3 of them have not been verified. At this time, the verification personnel can modify or improve the test template according to the 3 unverified functions.

In order to improve the efficiency of chip verification, the framework of FIG. 1 can be modified in the solution of this embodiment, to avoid excessive manual modification and perfection by verification personnel, so as to improve verification efficiency and verification accuracy.

The verification framework diagram implemented in the embodiment of the present application may be as shown in FIG. 2 and includes an adaptive instruction generator including an adaptive expert system controller, a random value generator, an instruction generation module, and a performance monitoring unit counter. The adaptive expert system controller includes a test template and a control parameter template. The test template includes an instruction set and instruction constraints. The control parameter template includes a control parameter set. The control parameters in the control parameter set are used to control different instructions in the instruction sequence. The specific parameters used during operation can be the addresses that need to be accessed on the chip to be generated according to the control parameters; the random number generator can randomly generate "seeds", and the instruction constraints and "seeds" in the instruction constraints It can generate multiple instruction index values, and the instruction generation module indexes multiple instructions in the instruction set according to the multiple instruction index values to generate the instruction sequence; the performance monitoring unit counter can automatically count whether the test coverage rate of the instruction sequence when the chip to be verified runs The preset value, if the preset value can be reached, the counter of the performance monitoring unit is triggered to increase by 1.

Based on the verification framework shown in FIG. 2, an embodiment of the present application provides a chip verification method, which is applicable to the adaptive instruction generator shown in FIG. 2. Referring to FIG. 3, a verification provided by an embodiment of the present application The specific process of the chip method includes:

Step 300: Determine a random value.

In an alternative embodiment, the random number generator in the adaptive command generator randomly generates a random value, and based on the random value, selects the corresponding command sequence from the test template in the adaptive command generator, in After generating a simulation test instruction use case according to the instruction sequence and the default control parameters, let the chip to be verified run the simulation test instruction use case, and after the chip to be verified runs the simulation test instruction use case, determine that the chip to be verified runs the simulation test Whether the test coverage obtained when instructing the use case is greater than a preset value, and if it is greater than the preset value, the random value is used as the random value determined in step 300.

Exemplarily, the default control parameter may be a control parameter in a preset control parameter set. Specifically, the adaptive expert system controller can read the default control parameters in the chip to be verified according to the storage address of the default control parameters.

Obtaining the test coverage of the chip to be verified after running the simulation test instruction use case can be obtained in at least one of the following three ways:

Method 1: Use the MRS (move to general) purpose register from the system register in the adaptive expert system controller to read the PMU (performance monitors unit) register to obtain test coverage ;

Method 2: Use the MRS instruction in the adaptive expert system controller to read special registers to obtain test coverage;

Method 3: Use the load instruction in the adaptive expert system controller to read the memory of the chip to be verified to obtain the test coverage.

It should be noted that when the MRS instruction is used to read the PMU register to obtain the test coverage, the test coverage information obtained by running the simulation test instruction use case of the chip to be verified will be stored in the PMU register; the MRS instruction is used to read the special register When the test coverage is obtained by way, the test coverage information obtained by the chip to be verified running the simulation test instruction use case will be stored in the special register. Since each special register has a clear function, the MRS read has the function of storing the test coverage You can obtain the test coverage by using the special register of the test; when you use the load instruction to read the memory of the chip to be verified to obtain the test coverage, the test coverage information obtained by the chip to be verified running the simulation test instruction use case will be stored in the In the memory of the chip to be verified, when this method is used to obtain test coverage, there is no need to add new PMU registers and special registers, which can save resources.

In an optional embodiment, a corresponding instruction sequence is selected from the test template based on a random value, and multiple instruction index values may be calculated based on the random value first, and then based on the calculated multiple instruction index values in the adaptive In the test template of the command generator, select the corresponding command sequence.

In order to facilitate understanding of the selection of the corresponding instruction sequence according to the random value, an example will be described below.

As shown in FIG. 4, it is a schematic diagram of a process of selecting a corresponding instruction sequence according to a random value provided by an embodiment of the present application. In Figure 4, X is a selected random value, X can be a 64-bit hexadecimal number, based on the preset first function Y = f1 (X), respectively calculated a series of digital sequences (Y1, Y2, Y3 ….Yn), where X1 is obtained based on X, X is used as the initial input value of the function Y=f1(X), and in the subsequent calculation of Y2, Y3….Yn, the value of the last calculation result is used as a function each time Y = input value of f1(X). Then take the number sequence (Y1, Y2, Y3...Yn) as the sequence of instruction index values, and calculate the instruction Z that can be indexed in the test template for each instruction index value Y based on the preset second function Z = f2 (Y) Therefore, the instruction sequence (Z1, Z2, Z3...Zn) can be indexed in the test template according to the instruction index value sequence (Y1, Y2, Y3...Yn).

It should be noted here that a set of number sequences is calculated based on a random number using a preset algorithm, and the preset algorithm Y=f1(X) here may be obtained according to instruction constraints.

In an optional embodiment, after the performance monitoring unit counter obtains the test coverage obtained when the chip to be verified runs the simulation test instruction use case is greater than a preset value, the adaptive command generator may control the chip to be verified to continue to run The simulation test instruction use case M times. After determining that there are N test coverages greater than a preset value in the obtained M test coverages, the generated random value is finally used as the random value determined in step 300 above. M is greater than or equal to N. In this way, it can ensure that the selected random value is more excellent, which can be defined as a good random value or a good "seed".

For example, if the preset value is 80%, M is 5, and N is 3, after the test coverage obtained by running a simulation test command use case of the chip to be verified is 90%, the chip to be verified can be controlled to continue to run the simulation test Instruct the use case 5 times, and the 5 test coverages obtained are 85%, 88%, 90%, 91%, 79%. Since 4 of the 5 test coverages obtained are greater than the preset value of 80%, you can The random value of the instruction sequence that generates the simulation test instruction use case is regarded as a good random value, that is, a good "seed". The good "seed" can then be used as the real "seed" used in generating actual test instruction use cases.

Step 301: The adaptive expert system controller selects a corresponding instruction sequence in a test template based on the random value, and the test template includes multiple instructions.

After the random value is determined, the corresponding instruction sequence is selected in the test template based on the random value. Here, the process of selecting the corresponding instruction sequence in the test template based on the random value and selecting a random value from the test template based on the random value The process of the corresponding instruction sequence is the same, and will not be repeated here.

Step 302: The adaptive expert system controller repeats the following steps based on the selected instruction sequence:

Traverse a control parameter in the set of preset control parameters that has not been traversed, and generate an actual test command use case based on the selected command sequence and the control parameters obtained by the traversal; obtain the test obtained when the actual test command use case is run by the chip to be verified When the coverage rate is greater than the preset value, the chip to be verified is controlled to run the instruction use case multiple times, and if a bug occurs, it ends, otherwise, the step of traversing a control parameter in the preset control parameter set that has not been traversed is executed again.

Different control parameters in the preset control parameter set here can be preset according to different functions of the chip to be verified, for example, for the chip A to be verified, some control parameters of the chip A to be verified can be preset, when verifying the chip A to be verified, Store some control parameters preset for the chip A to be verified in the preset control parameter set; some control parameters of the chip B to be verified will be preset for the chip B to be verified. When verifying the chip B to be verified, the preset control parameters The set stores some control parameters preset for the chip B to be verified.

Traverse a control parameter in the preset control parameter set that has not been traversed, that is, each time a real test command use case is generated according to the selected command sequence and control parameter, the control parameter is in the preset control parameter set A control parameter that has not been used before the actual test instruction use case is generated this time. This is to prevent the chip to be verified from repeatedly running some of the same instruction use cases and avoid wasting time.

After generating an actual test instruction use case, let the chip to be verified run the actual test instruction use case to obtain the test coverage obtained after the chip to be verified runs the actual test instruction use case. Here, the test coverage obtained by the chip to be verified running the instruction use case is obtained The rate is the same as the above method for obtaining the test coverage after the use case of the simulation test instruction to be verified by the chip to be verified, which will not be repeated here.

In a possible implementation manner, when a chip to be verified runs an actual test instruction use case, if a bug occurs, the random value of the instruction sequence that generates the actual test instruction use case may be stored in a random number set, and the random number set The random number in can be used to provide excellent random numbers when verifying other target chips, which can save time for verifying other target chips.

In an optional embodiment, if the control parameters that are not traversed cannot be traversed in the preset control parameter set, it may return to the step of determining other random values, and then repeat

steps

301 and 302, Until the chip to be verified has a bug.

The method for verifying the chip provided above first determines a random value, then selects the corresponding command sequence based on the random value, then traverses the control parameters, and generates an actual test command use case according to the command series and the traversed control parameters, when to be verified When the test coverage obtained by the chip running the actual test command case is greater than the preset value, the chip to be verified is controlled to run the actual test command use case multiple times. If a bug occurs, the verification is stopped, and if there is no bug, the control parameters are continued to be traversed. The preset conditions cyclically verify the chip to be verified, so that no personnel is required to participate, the operation is simple, and the verification efficiency can be improved.

Based on the embodiment shown in FIG. 3 above, an embodiment of the present application also provides a flowchart of a complete method for chip verification. Referring to FIG. 5, the flowchart of this example may specifically include:

Step 500: The random number generator randomly selects a random number X, based on the random number X, uses a preset algorithm to calculate a set of digital sequences, which can be used as an instruction index value sequence, and then uses the instruction index value sequence from the test The corresponding instructions are selected in sequence from the template to form an instruction sequence;

In step 501, the adaptive expert system controller combines the obtained command sequence (Z1, Z2, Z3...Zn) with the default control parameters to generate a simulation test command use case. Specifically, it can be read from the storage address according to the default control parameters The default control parameters, and then use the default control parameters and the instruction sequence obtained above (Z1, Z2, Z3...Zn) to generate the simulation test instruction use case, and then let the target chip run the simulation test instruction use case;

Step 502, the performance monitoring unit counter obtains the test coverage rate output by the target chip after running the simulation test instruction use case;

In step 503, the counter of the performance monitoring unit determines whether the test coverage output by the target chip after running the simulated test instruction use case is greater than a preset value. If so, step 504 is executed; otherwise, in step 500, the adaptive expert system controller triggers a random command The generator randomly selects other values of X and continues to perform steps 500 to 502; it should be noted here that the random number X returned to step 500 is the X that has not been selected before, such as the first step based on the selected X1. After 500 to step 502, if step 500 is returned to again, X2 is selected, and steps 500 to 502 are executed again based on X2.

Determine whether a simulation test instruction use case is a good simulation test instruction use case for target chip verification. One of the criteria for the determination is whether the test coverage obtained when the target chip runs the simulation test instruction use case reaches a preset value, if it can be achieved The preset value indicates that the simulation test instruction use case is a good simulation test instruction use case. For example, the target chip runs a simulation test instruction use case to obtain a test coverage of 10%, which means that it is necessary to verify the target chip The function of verification The simulation test command use case is only verified to 10%. If a random value in the simulation test command use case with a test coverage rate of 10% is used to generate the instruction sequence, the actual test generated by the instruction sequence and the traversed control parameters is used to generate the instruction sequence. The instruction use case verifies whether the chip has bugs, and the verification efficiency is low, so it is necessary to first determine that the simulation test instruction use case is a better simulation test instruction use case.

Step 504, the adaptive expert system controller continues to control the target chip to run the simulation test instruction use case M times, and the performance monitoring unit counter obtains M test coverage results respectively output by the M runs;

Step 505, if there are N test coverage results among the M test coverage results that are all greater than the preset value, then step 506 is executed; otherwise, return to step 500, the adaptive expert system controller triggers the random command generator to randomly select other X After the value, continue to perform steps 500 to 502; here it needs to be explained that the random number X returned to step 500 is the X that has not been selected before. For example, after performing step 500 to step 502 based on the selected X1 for the first time, If you return to step 500 again, X2 will be selected, and steps 500 to 502 will be executed again based on X2.

Where M>=N, for example, M may be 5, and N may be 3.

It should be noted here that in step 503, the adaptive expert system controller determines whether the simulated test instruction use case is a good simulated test instruction use case according to the state of the performance monitoring unit counter. If the performance monitoring unit counter is increased by 1, then It can be determined that the simulation test instruction use case is a good simulation test instruction use case. Since the target chip only runs the simulation test instruction use case once, in order to further determine that the simulation test instruction use case is indeed a better simulation test instruction use case, so Continue to control the target chip to run the simulation test instruction use case M times. If there are N results out of the M test coverage results obtained that are greater than a preset value, the simulation test instruction use case is determined to be a better instruction use case.

Step 506, the adaptive expert system controller triggers the random command generator to re-execute the operation in step 500 according to the random number X, index the command sequence (Z1, Z2, Z3...Zn) in the test template, and judge the control parameters Whether a control parameter that has not been traversed can be traversed in the collection, which can specifically be judged whether a storage address that has not been traversed can be traversed in the address set of the storage address corresponding to each control parameter, and if so, step 507 is executed, Otherwise, returning to step 500, the adaptive expert system controller triggers the random command generator to randomly select other values of X, and then continues to perform steps 500 to 502; it should be noted here that returning to the random number X selected in step 500 is not previously done. The selected X, for example, after performing steps 500 to 502 based on the selected X1 for the first time, if step 500 is returned to again, X2 is selected, and steps 500 to 502 are executed again based on X2.

Step 507, the adaptive expert system controller generates an actual test instruction use case based on the instruction sequence (Z1, Z2, Z3...Zn) and the traversed control parameters;

Step 508, after the adaptive expert system controller controls the target chip to run the actual test instruction use case, the performance monitoring unit counter obtains the test coverage rate output by the target chip to run the actual test instruction use case;

In step 509, the counter of the performance monitoring unit determines whether the test coverage rate output by the target chip after running the actual test instruction use case is greater than a preset value. If yes, step 510 is executed; otherwise, step 506 is returned to;

Step 510, the adaptive expert system controller continues to control the target chip to run the actual test instruction use case K times;

In step 511, the adaptive expert system controller determines whether a bug occurs in the actual test instruction use case when the target chip runs K times, and if yes, the test ends; otherwise, returns to step 506.

After performing the above step 504, if there are N test coverage results among the M test coverage results that are all greater than a preset value, the selected random value X may be stored, or may be corresponding to the selected random value X The storage address of the storage, so that in the subsequent testing of other chips, these good random values can be preferentially stored, or the good random values can be obtained according to the storage address of the stored priority random values, thereby reducing the cost of finding good random values Time to improve the efficiency of finding good random values.

Based on the verification framework shown in FIG. 2, an embodiment of the present application also provides a chip verification method, which is applicable to the adaptive instruction generator shown in FIG. 2. Referring to FIG. 6, another method provided by the embodiment of the present application The specific process of a method for verifying a chip includes:

Step 600: Determine a control parameter.

In an optional embodiment, the adaptive expert system controller first randomly selects a control parameter, uses the corresponding random value to select the corresponding instruction sequence in the test template, and generates a simulation test based on the instruction sequence and the control parameter Instruction use case; when the test coverage obtained when the chip to be verified obtained by the performance monitoring unit counter runs the simulation test instruction use case is greater than a preset value, the selected control parameter is used as the control parameter determined in step 600.

Exemplarily, a randomly selected control parameter may be selected from a preset control parameter set. For different chips to be verified, the control parameters in the preset control parameter set may be different.

In an optional embodiment, using a corresponding random value to select a corresponding instruction sequence from the test template, a plurality of instruction index values may be calculated based on an unused random value, and then based on the calculated plurality of instruction indexes The value selects the corresponding command sequence in the test template of the adaptive command generator.

The corresponding random value here may be a randomly generated random value that has not been used before.

Here, the test coverage rate of the chip to be verified after running the simulation test instruction use case is the same as the method of obtaining the test coverage rate of the chip to be verified after running the analog test instruction use case in the method of FIG. 3, and details are not repeated here.

In an alternative embodiment, after the performance monitoring unit counter obtains the test coverage obtained when the chip to be verified runs the simulation test instruction use case is greater than a preset value, the adaptive command generator may control the chip to be verified to run the Simulate test command use cases M times, after determining that there are N test coverages greater than a preset value in the obtained M test coverages, then finally use the control parameters in the simulation test command use cases as the control parameters determined in step 600 above, Here, M is greater than or equal to N. In this way, the selected control parameter can be guaranteed to be more excellent, and can be defined as an excellent control parameter.

Step 601: Select a corresponding instruction sequence in a test template based on an unused random value. The test template includes multiple instructions.

In an optional embodiment, a plurality of instruction index values are calculated based on an unused random value, and a corresponding instruction sequence is selected in the test template based on the calculated plurality of instruction index values.

Step 602: Generate an actual test instruction use case according to the selected instruction sequence and the control parameter.

The purpose of generating actual test instruction use cases here is to let the target chip run the actual test instruction use cases to obtain test coverage. Similarly, the test coverage is obtained in the same way as in FIG. The coverage method is the same, and will not be repeated here.

Step 603: The performance monitoring unit counter obtains the test coverage obtained when the target chip runs the actual test instruction use case when it is greater than a preset value, and the adaptive expert system controller controls the target chip to run the actual test instruction use case multiple times, if If there is a bug, it is over, otherwise the step of selecting the corresponding instruction sequence based on other unused random values is executed again.

In a possible implementation manner, when a bug occurs when the chip to be verified runs the actual test instruction use case, the control parameter that generates the actual test instruction use case may be marked in the preset control parameter set, and the preset control parameter set The control parameters marked in can be used to provide excellent control parameters when verifying other target chips, which can save time for verifying other target chips.

Another method for verifying the chip provided above first determines a control parameter, then generates an actual test command use case based on an unused random value and the control parameter, and obtains test coverage obtained by running the actual test command use case for the chip to be verified After the rate is greater than the preset value, control the chip to be verified to run the actual test instruction use case multiple times. If there is a bug, stop the verification. If there is no bug, continue to use other unused random values to select the corresponding instruction sequence. Some preset conditions cyclically verify the chip to be verified, so that no personnel is needed, the operation is simple, and the verification efficiency can be improved.

Based on the embodiment shown in FIG. 6 above, the embodiment of the present application further provides a flowchart of another complete method of chip verification. Referring to FIG. 7, the flowchart of this example may specifically include:

Step 700: The adaptive expert system controller randomly selects a control parameter P from the preset control parameter set; specifically, it may randomly select a storage address from the address set of the storage address corresponding to each control parameter, and store the selected storage address according to the selected storage The address obtains the control parameter P;

Step 701: The random number generator randomly selects a random number X, and based on the random number X, a set of number sequences is calculated using a preset algorithm, and the set of number sequences can be used as an instruction index value sequence, and then the instruction generation module uses the instruction index value The sequence selects the corresponding instructions in sequence from the test template to form an instruction sequence;

Step 702: The adaptive expert system controller combines the obtained instruction sequence (Z1, Z2, Z3...Zn) with the control parameter P to generate a simulation test instruction use case, and then controls the target chip to run the simulation test instruction use case;

Step 703: The performance monitoring unit counter obtains the test coverage rate output by the target chip after running the simulation test instruction use case;

Step 704: The performance monitoring unit counter determines whether the test coverage output by the target chip after running the simulation test instruction use case is greater than a preset value. If so, step 705 is performed; otherwise, steps 710-711-702 are performed, using the generated in step 700 Random value X and randomly selected other control parameters P generate simulation test command use cases; it should be noted here that the random control parameter P selected in step 711 is P that has not been selected before, such as selecting P1 in step 701, If step 710 is executed, P2 will be selected.

Step 705: The adaptive expert system controller continues to let the target chip run the simulation test instruction use case M times, and the performance monitoring unit counter obtains M test coverage results respectively output by the M runs.

Step 706: If there are N test coverage results among the M test coverage results that are all greater than a preset value, determine that the previously randomly selected control parameter P is a good control parameter, and if the control parameter P is fixed, step 707 is performed; otherwise Perform steps 710 to 711 to 702, use the random value X generated in step 700 and randomly selected other control parameters P to generate a simulation test command use case; here it needs to be noted that the random control parameter P selected in step 711 is not previously available The selected P, for example, P1 is selected in step 701, and if step 710 is executed, P2 is selected.

Where M>=N, for example, M may be 5, and N may be 3.

Step 707, the random number generator re-executes the operation in step 700, that is, re-randomly selects other numbers X that have not been previously selected. It should be noted here that the random number X selected in step 700 is not selected before. X, such as X1 selected in step 700 for the first time, if step 700 is executed again, X2 will be selected, and a new instruction sequence (Z1, Z2, Z3....Zn)' will be re-indexed in the test template based on X2, and Combine the re-indexed new instruction sequence with the determined good control parameters P to generate actual test instruction use cases, control the target chip to run the actual test instruction use cases to obtain test coverage, and determine whether the test coverage is greater than the pre-test Set value, if yes, go to step 708; otherwise return to step 701, randomly select other random value X and continue to perform steps 702 to 706; it needs to be explained here that returning to the other random value X selected in step 701 is not before The selected X, for example, selects X1 for the first time, and if it returns to step 701 again, X2 will be selected.

Step 708: The adaptive expert system controller continues to control the target chip to run the actual test instruction use case K times;

Step 709: The adaptive expert system controller determines whether there is a bug in the actual test instruction use case when the target chip runs K times, and if so, the test ends; otherwise, returns to step 700;

Step 710. The instruction generation module uses the random number X in step 701 to generate an instruction use case;

Step 711: The adaptive expert system controller randomly generates unused control parameters P.

After performing step 706 above, if N test coverage results out of the M test coverage results are all greater than the preset value, the control parameter P may be marked in the preset control parameter set, or the parameter set The storage address corresponding to the control parameter P in the corresponding address set is marked, so that in subsequent verification of other chips, the control parameter with the mark in the preset control parameter set may be preferentially selected, or the preset The storage address with a mark in the address set corresponding to the parameter set obtains the excellent control parameters according to the selected storage address, thereby reducing the time spent in searching for the excellent control parameters and improving the efficiency of finding the excellent control parameters.

The embodiments of the present application provide two methods for verifying the chip. Both methods need to set some preset conditions to cyclically verify the chip, thereby eliminating the need for personnel to participate and improving the verification efficiency.

Based on the above embodiments, the embodiments of the present application further provide an apparatus for implementing the method for verifying a chip as shown in FIG. 3 or FIG. 5. Referring to FIG. 8, the device 800 includes: a processing unit 801 and a storage unit 802, wherein the storage unit 802 is used to store program code; and the processing unit 801, when the program code is executed by the processing unit 801 When the processing unit 801 can perform the steps 300 to 302 shown in FIG. 3, or the steps 500 to 511 shown in FIG. 5, or the processing unit 801 can perform the steps shown in FIG. 600 to step 603, or perform steps 700 to 711 shown in FIG.

Using the device provided by the embodiment of the present application, a random value is determined, and then the corresponding instruction sequence is selected based on the random value, and the following steps are repeatedly performed based on the instruction sequence: first, traverse a control parameter that has not been traversed, and then according to the selected instruction The control parameters obtained through the sequence and traversal generate an actual test command use case; when the test coverage obtained when the chip is run from the actual test command use case is greater than a preset value, the chip is run the actual test command use case multiple times, if a defect occurs The bug ends, otherwise, the step of traversing a control parameter that has not been traversed in the preset control parameter set is performed again. In this way, when verifying the chip, verification can be performed cyclically according to preset conditions, without the need for human involvement, and the operation is simple, thereby improving verification efficiency.

Or, using the device provided in the embodiment of the present application, determine a control parameter, and then select corresponding instruction sequences based on different random values, and repeat the following steps based on each selected instruction sequence: generate an actual test instruction with the determined control parameters Use case; when the test coverage obtained when the chip runs the actual test instruction use case is greater than the preset value, make the chip run the actual test instruction use case multiple times, if there is a defect bug, it will end, otherwise use another random value to determine The combination of the instruction sequence and the control parameters generates the actual test instruction use case steps. In this way, when verifying the chip, verification can be performed cyclically according to preset conditions, without the need for human involvement, and the operation is simple, thereby improving verification efficiency.

It should be noted that the division of the units in the embodiments of the present application is schematic, and is only a division of logical functions. In actual implementation, there may be another division manner. The functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units may be integrated into one unit. The above integrated unit may be implemented in the form of hardware or software functional unit.

If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it may be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application essentially or part of the contribution to the existing technology or all or part of the technical solution can be embodied in the form of a software product, the computer software product is stored in a storage medium , Including several instructions to enable a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute all or part of the steps of the methods described in the embodiments of the present application. The aforementioned storage media include: U disk, mobile hard disk, read-only memory (ROM), random access memory (random access memory, RAM), magnetic disk or optical disk and other media that can store program codes .

Based on the above embodiment, an embodiment of the present application further provides an apparatus. Referring to FIG. 9, the apparatus 900 includes: a processor 901, and optionally, a memory 902. The processor 901 may be a central processor (central processing unit, CPU), network processor (network processor, NP) or a combination of CPU and NP. The processor 901 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD) or a combination thereof. The PLD may be a complex programmable logic device (complex programmable logic device (CPLD), a field programmable logic gate array (field-programmable gate array, FPGA), a general array logic (generic array logic, GAL), or any combination thereof.

The processor 901 and the memory 902 are connected to each other. Optionally, the processor 901 and the memory 902 are connected to each other through a bus 903; the bus 903 may be a peripheral component interconnection standard (Peripheral Component Interconnect, PCI) bus or an extended industry standard architecture (Extended Industry Standard Architecture) , EISA) bus and so on. The bus can be divided into an address bus, a data bus, and a control bus. For ease of representation, only a thick line is used in FIG. 9, but it does not mean that there is only one bus or one type of bus.

The device shown in FIG. 9 may be the adaptive command generator in FIG. 2 or a control component or control unit in the adaptive command generator in FIG. 2. The processing unit 801 in FIG. 8 described above may be implemented based on the processor 901 herein, and the storage unit 802 may be implemented based on the memory 902 herein. For specific functions and execution principles of the processor 901 and the memory 902, please refer to the detailed description of the foregoing method embodiments, and details are not repeated here.

Those skilled in the art should understand that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware. Moreover, the present application may take the form of a computer program product implemented on one or more computer usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer usable program code.

This application is described with reference to flowcharts and/or block diagrams of methods, devices (systems), and computer program products according to embodiments of the application. It should be understood that each flow and/or block in the flowchart and/or block diagram and a combination of the flow and/or block in the flowchart and/or block diagram may be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, special-purpose computer, embedded processing machine, or other programmable data processing device to produce a machine that enables the generation of instructions executed by the processor of the computer or other programmable data processing device An apparatus for realizing the functions specified in one block or multiple blocks of one flow or multiple flows of a flowchart and/or one block or multiple blocks of a block diagram.

These computer program instructions may also be stored in a computer-readable memory that can guide a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture including an instruction device, the instructions The device implements the functions specified in one block or multiple blocks of the flowchart one flow or multiple flows and/or block diagrams.

These computer program instructions can also be loaded onto a computer or other programmable data processing device, so that a series of operating steps are performed on the computer or other programmable device to produce computer-implemented processing, which is executed on the computer or other programmable device The instructions provide steps for implementing the functions specified in one block or multiple blocks of the flowchart one flow or multiple flows and/or block diagrams.

Obviously, those skilled in the art can make various modifications and variations to the embodiments of the present application without departing from the scope of the embodiments of the present application. In this way, if these modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application is also intended to include these modifications and variations.

Claims

A chip verification method is characterized by including:

Determine a random value;

Select a corresponding instruction sequence in the test template based on the random value, the test template includes multiple instructions;

Repeat the following steps based on the instruction sequence:

Traverse a control parameter in the preset control parameter set that has not been traversed, and generate an actual test command use case according to the selected instruction sequence and the control parameter obtained by traversing;

When the test coverage obtained when the first chip runs the actual test instruction use case is greater than a preset value, the first chip is controlled to run the actual test instruction use case multiple times, and if there is a defect bug, it ends, otherwise the traversal is performed again A step of a control parameter in the preset control parameter set that has not been traversed.
The method of claim 1, wherein the determining a random value comprises:

Randomly generate a random value;

Select a corresponding instruction sequence in the test template based on the random value, and generate a simulation test instruction use case according to the selected instruction sequence and default control parameters;

When the test coverage obtained when the first chip runs the simulation test instruction use case is greater than a preset value, the generated random value is used as a determined random value.
The method according to claim 1 or 2, wherein the selecting a corresponding instruction in the test template based on the random value to obtain an instruction sequence includes:

A plurality of instruction index values are calculated based on the random value, and a corresponding instruction sequence is selected in the test template based on the calculated plurality of instruction index values.
The method according to any one of claims 1 to 3, characterized in that, if the step of traversing a control parameter in the preset control parameter set that has not been traversed is performed again, the method further includes:

If the control parameters that are not traversed cannot be traversed in the control parameter set, then return to the step of determining other random values.
The method according to claim 2, wherein before using the generated random value as a determined random value, the method further comprises:

When the test coverage obtained when the first chip runs the simulation test instruction use case is greater than a preset value, control the first chip to run the simulation test instruction use case M times to obtain M test coverages respectively;

It is determined that at least N of the M test coverage ratios are greater than a preset value; both M and N are positive integers, and M>=N.
The method according to claim 1 or 2, further comprising:

If a bug occurs, the determined random value is stored in a random number set, and the random number set is used to provide a random value when verifying the second chip.
The method of claim 2, wherein the default control parameter is a control parameter in the preset control parameter set.
The method according to any one of claims 1 to 7, wherein the test coverage is determined by at least one of the following ways:

Use the read system status register to general register MRS instruction to read the performance monitoring unit PMU register to obtain the test coverage, as the test coverage of the first chip to run the actual test instruction use case; or

Use the MRS instruction to read the special register to obtain the test coverage, as the test coverage of the first chip running the actual test instruction use case; or

A load instruction is used to read the memory of the first chip to obtain a test coverage, which is used as the test coverage of the first chip to run the actual test instruction use case.
A chip verification method is characterized by including:

Determine a control parameter;

Select a corresponding instruction sequence in a test template based on an unused random value, the test template includes multiple instructions;

Generating an actual test instruction use case according to the selected instruction sequence and the control parameters;

When the test coverage obtained when the first chip runs the actual test instruction use case is greater than a preset value, the first chip is controlled to run the actual test instruction use case multiple times, and if a bug occurs, it is ended, otherwise the execution based on other The unused random values select the steps of the corresponding instruction sequence.
The method of claim 9, wherein the determining a control parameter comprises:

Randomly select a control parameter;

Use a corresponding random value to select a corresponding instruction sequence in the test template, and generate a simulation test instruction use case based on the instruction sequence and the control parameters;

When the test coverage obtained when the first chip runs the simulation test instruction use case is greater than a preset value, the selected control parameter is used as a determined control parameter.
The method according to claim 9 or 10, wherein the selecting a corresponding instruction sequence in the test template based on an unused random value includes:

A plurality of instruction index values are calculated based on an unused random value, and a corresponding instruction sequence is selected in the test template based on the calculated plurality of instruction index values.
The method according to claim 10, wherein before using the selected control parameter as a determined control parameter, the method further comprises:

When the test coverage obtained when the first chip runs the simulation test instruction use case is greater than a preset value, control the first chip to run the simulation test instruction use case M times, and obtain M test coverages respectively;

It is determined that at least N of the M test coverage ratios are greater than a preset value; both M and N are positive integers, and M>=N.
The method according to claim 9 or 10, further comprising:

If a bug occurs, the determined control parameters are stored in a control parameter set, which is used to provide control parameters when verifying the second chip.
The method according to any one of claims 9 to 13, wherein the test coverage is determined by at least one of the following ways:

Use the read system status register to general register MRS instruction to read the performance monitoring unit PMU register to obtain the test coverage, as the test coverage of the first chip to run the actual test instruction use case; or

Use the MRS instruction to read the special register to obtain the test coverage, as the test coverage of the first chip running the actual test instruction use case; or

A load instruction is used to read the memory of the first chip to obtain a test coverage, which is used as the test coverage of the first chip to run the actual test instruction use case.
An apparatus is characterized by comprising: a processor and a memory, the processor and the memory are coupled;

The memory is used to store computer programs;

The processor is configured to execute a computer program stored in the memory to cause the device to execute determining a random value; based on the random value, a corresponding instruction sequence is selected in a test template, and the test template includes multiple instructions ; Repeat the following steps based on the instruction sequence: traverse a control parameter in the preset control parameter set that has not been traversed, and generate an actual test instruction use case according to the selected instruction sequence and the control parameters obtained by traversal; When the test coverage obtained when the first chip runs the actual test instruction use case is greater than a preset value, the first chip is controlled to run the actual test instruction use case multiple times, and if the first chip has a defect bug, it ends, otherwise The step of traversing a control parameter that has not been traversed in the preset control parameter set is performed again.
The apparatus according to claim 15, wherein the processor is specifically used to:

Randomly generate a random value;

Select a corresponding instruction sequence in the test template based on the random value, and generate a simulation test instruction use case according to the selected instruction sequence and default control parameters;

When the test coverage obtained when the first chip runs the simulation test instruction use case is greater than a preset value, the generated random value is used as a determined random value.
The device according to claim 15 or 16, wherein when the processor selects the corresponding instruction sequence in the test template based on the random value, it is specifically used to:

A plurality of instruction index values are calculated based on the random value, and a corresponding instruction sequence is selected in the test template based on the calculated plurality of instruction index values.
The apparatus according to any one of claims 15 to 17, wherein the processor is further used to:

If the control parameters that are not traversed cannot be traversed in the control parameter set, then return to the step of determining other random values.
The apparatus of claim 16, wherein the processor is further configured to:

Before using the generated random value as a determined random value, after obtaining the test coverage obtained when the first chip runs the simulation test instruction use case is greater than a preset value, control the first chip to run the simulation test instruction Use cases M times, get M test coverage respectively;

It is determined that at least N of the M test coverage ratios are greater than a preset value; both M and N are positive integers, and M>=N.
The apparatus according to claim 15 or 16, wherein the processor is further used to:

If the first chip has a bug, the determined random value is stored in a random number set, and the random number set is used to provide a random value when verifying the second chip.
The device according to any one of claims 15 to 20, wherein the test coverage is determined by at least one of the following ways:

The processor uses the read system status register to general register MRS instruction to read the performance monitoring unit PMU register to obtain the test coverage, as the test coverage of the first chip running the actual test instruction use case; or

The processor uses the MRS instruction to read the special register to obtain the test coverage, which is used as the test coverage of the first chip to run the actual test instruction use case; or

The processor uses the load instruction to read the memory of the first chip to obtain the test coverage, which is used as the test coverage of the first chip to run the actual test instruction use case.
An apparatus is characterized by comprising: a processor and a memory, the processor and the memory are coupled;

The memory is used to store computer programs;

The processor is configured to execute a computer program stored in the memory to cause the device to execute determining a control parameter; select a corresponding instruction sequence in a test template based on an unused random value, and the test template Including a plurality of instructions; generating an actual test instruction use case according to the selected instruction sequence and the control parameters; when the test coverage obtained when the first chip runs the actual test instruction use case is greater than a preset value, controlling the first A chip runs the actual test instruction use case multiple times, and ends if the first chip has a bug, otherwise it executes the step of selecting the corresponding instruction sequence based on other unused random values.
The apparatus of claim 22, wherein the processor is specifically used to:

Randomly select a control parameter;

Use the corresponding random value to select the corresponding instruction sequence in the test template, and generate a simulation test instruction use case based on the instruction sequence and the control parameters; when the first chip is acquired to run the simulation test instruction use case, the test coverage obtained is greater than When the value is preset, the selected control parameter is used as a determined control parameter.
The device according to claim 22 or 23, characterized in that when the processor selects the corresponding instruction sequence in the test template based on an unused random value, it is specifically used to:

A plurality of instruction index values are calculated based on an unused random value, and a corresponding instruction sequence is selected in the test template based on the calculated plurality of instruction index values.
The apparatus of claim 23, wherein the processor is further configured to:

Before using the selected control parameter as a determined control parameter, after obtaining the test coverage obtained when the first chip runs the simulation test instruction use case is greater than a preset value, control the first chip to run the simulation test Instruction M use cases M times, respectively obtained M test coverage;

It is determined that at least N of the M test coverage ratios are greater than a preset value; both M and N are positive integers, and M>=N.
The apparatus according to claim 24 or 25, wherein the processor is further used to:

If the first chip has a bug, the determined control parameters are stored in a control parameter set, and the control parameter set is used to provide control parameters when verifying the second chip.
The device according to any one of claims 22 to 26, wherein the test coverage is determined by at least one of the following ways:

The processor uses the read system status register to general register MRS instruction to read the performance monitoring unit PMU register to obtain the test coverage, as the test coverage of the first chip running the actual test instruction use case; or

The processor uses the MRS instruction to read the special register to obtain the test coverage, which is used as the test coverage of the first chip to run the actual test instruction use case; or

The processor uses the load instruction to read the memory of the first chip to obtain the test coverage, which is used as the test coverage of the first chip to run the actual test instruction use case.
A computer-readable storage medium, characterized in that it includes a program or instruction, and when the program or instruction runs on a computer, the method according to any one of claims 1-14 is executed.