CN113168364A - Chip verification method and device - Google Patents

Chip verification method and device Download PDF

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Publication number
CN113168364A
CN113168364A CN201880099920.XA CN201880099920A CN113168364A CN 113168364 A CN113168364 A CN 113168364A CN 201880099920 A CN201880099920 A CN 201880099920A CN 113168364 A CN113168364 A CN 113168364A
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Prior art keywords
test
instruction
chip
control parameter
coverage rate
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CN201880099920.XA
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Chinese (zh)
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杨鸿志
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/263—Generation of test inputs, e.g. test vectors, patterns or sequences ; with adaptation of the tested hardware for testability with external testers
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318385—Random or pseudo-random test pattern
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31707—Test strategies

Abstract

The application provides a chip verification method and device, which are used for solving the problems that in the prior art, personnel is needed to participate when a bug exists in a verification chip, the operation is complex, and the verification efficiency is low. In the first mode, a corresponding instruction sequence is selected based on the determined random numerical value, and the step meeting the conditions is repeatedly executed; and after determining a control parameter, selecting an instruction sequence based on an unused random value and generating an actual instruction case according to the determined control parameter, and repeatedly executing the steps meeting the conditions. Therefore, in the chip verification process, personnel are not required, the operation is simple, and the verification efficiency can be improved.

Description

Chip verification method and device Technical Field
The present disclosure relates to the field of electronic technologies, and in particular, to a chip verification method and apparatus.
Background
With the development of large-scale integrated circuits and multi-thread multi-core processors, there is an increasing demand for verifying whether a chip has a problem, for example, verifying the cache of a Central Processing Unit (CPU) on a System On Chip (SOC) and the cache consistency of other devices in the SOC are one aspect of verifying whether the chip has a problem.
In the prior art, a constraint-based random test template mode is generally adopted to verify whether a chip has a problem, and the mode firstly defines a test template, wherein the test template comprises an instruction set and instruction constraints, then randomly generates an instruction combination to form an instruction sequence in the instruction set according to the instruction constraints, and generates an instruction case based on the instruction sequence and default control parameters, wherein the control parameters are parameters used for controlling different instructions in the instruction sequence to run. Therefore, different tested function values of the function points of the chip to be verified are output after the chip to be verified runs the command case, the test coverage rate is obtained according to the ratio of the number of the output function values to the number of the function values expected to be required, the verifier analyzes the test coverage rate, if the test coverage rate does not reach the expectation, the command set in the test template is modified according to the analysis result, for example, commands for testing functions corresponding to the function values which are not output in the command set are increased, the test coverage rate is further improved, the test coverage rate is improved, the chip to be verified runs the command case once through the chip to be verified, and the chip to be verified is proved to have no problem until the test coverage rate reaches the expectation and no defect (bug) occurs in the process of running the command case; and if the test coverage rate reaches the expectation and bug occurs in the process of operating the instruction use case, stopping verification, and repairing the defects of the chip to be verified by technical personnel according to the bug.
When the random test template based on the constraint verification method is adopted to verify whether the chip has problems or not, verification personnel is required to participate, the operation is more complicated, and the verification efficiency is lower.
Disclosure of Invention
The embodiment of the application provides a chip verification method and device, which are used for solving the problems that verification personnel are required to participate, the operation is complex and the verification efficiency is low when the chip is verified to have problems in the prior art.
In a first aspect, the present application provides a method for verifying a chip, comprising determining a random number; selecting a corresponding instruction sequence in a test template based on the random value, wherein the test template comprises a plurality of instructions; repeatedly executing the following steps based on the instruction sequence:
traversing an unexplored control parameter in a preset control parameter set, and generating an actual test instruction case according to the selected instruction sequence and the control parameter obtained by traversal;
and when the test coverage rate obtained when the first chip runs the actual test instruction case is larger than a preset value, controlling the first chip to run the actual test instruction case for multiple times, ending if a defect bug occurs, and otherwise, executing the step of traversing one control parameter which is not traversed in the preset control parameter set again.
In the method, after a random value is determined by a verification device or a part for verifying the chip, an instruction series is generated based on the random value, the instruction sequence and the traversed different control parameters respectively form different actual test instruction cases, then the chip to be verified (namely, a first chip) can be verified by using different actual test instruction cases generated based on different control parameters and the same instruction sequence, and when the test coverage rate obtained by the first chip running one actual test instruction case is greater than a preset value, the first chip can be further controlled to continue to run the actual test instruction case for multiple times until the chip to be verified is tested to have bug. Therefore, the verification efficiency of the chip can be improved, personnel are not needed to participate in the whole process, and the verification efficiency and the verification accuracy can be improved.
In one possible design, a random value may be randomly generated when determining the random value; selecting a corresponding instruction sequence in the test template based on the random numerical value, and generating a simulation test instruction case according to the selected instruction sequence and default control parameters; and when the test coverage rate obtained when the first chip runs the simulation test instruction case is larger than a preset value, taking the generated random value as the determined random value.
Because the test coverage rate obtained after the first chip runs the instruction case composed of the instruction sequence obtained based on the random value and the default control parameter is larger than the preset value, the random value can be determined to be a better random value, the better random value is used as the random number used for subsequently generating the actual test instruction case, and the test accuracy can be further improved.
In one possible design, the selecting a corresponding instruction in the test template based on the random value to obtain an instruction sequence includes: and calculating a plurality of instruction index values based on the random numerical value, and selecting a corresponding instruction sequence in the test template based on the plurality of instruction index values obtained by calculation.
In the method, how to obtain the instruction sequence based on the random numerical value is given, and the instruction index value obtained by calculating based on the random numerical value selects the corresponding instruction sequence, so that the method for selecting the instruction is simpler and is easy to operate.
In a possible design, if the control parameter which is not traversed in the control parameter set cannot be traversed, the execution may be returned to determine other random values, then the instruction sequence is continuously determined based on the determined other random values, the instruction sequence determined based on the other random values is combined with different control parameters to generate different actual test instruction cases, and the test is continuously performed on the first chip until the Bug is tested.
In the method, in the process of chip verification, if the control parameters cannot be traversed, the step of determining other random values is returned to enter the next new test cycle, so that the verification process can automatically run in a circulating manner.
In a possible design, after obtaining that the test coverage obtained when the first chip runs the simulation test instruction case is greater than a preset value, continuing to control the first chip to run the simulation test instruction case for M times to respectively obtain M test coverage; and when determining that at least N test coverage rates in the M test coverage rates are larger than a preset value, determining the generated random number value as a determined random number value, wherein M and N are positive integers, and M > -N.
Therefore, the determined random value can be ensured to be more optimized, and a good basis is provided for subsequently generating an actual test instruction case with a better test effect.
In a possible design, if a bug occurs in the first chip during the test, the determined random value may be stored in a random number set, and the random number set may be used to provide a random value when verifying the second chip.
Therefore, the verification chip proves that the selected random value is optimized, so that the selected random value is stored in the random number set, the random number set can continuously learn and accumulate excellent random values, and the excellent random values can be preferentially provided for verifying other chips (such as a second chip) so as to reduce the time for searching and determining the random values when the second chip is verified and further improve the verification efficiency.
In a possible design, the default control parameter may be one of the preset control parameter sets, or certainly may not be one of the preset control parameter sets, and the default control parameter may be selected as needed.
In one possible design, the test coverage may be determined, but is not limited to, by at least one of:
reading a PMU (power management unit) register of a performance monitoring unit by using a system state reading register to a general register MRS (parameter switching) instruction to obtain a test coverage rate which is used as the test coverage rate of the actual test instruction case run by the first chip; or
Using MRS instruction to read special register to obtain test coverage rate as the test coverage rate of the first chip for running the actual test instruction case; or
And reading the memory of the first chip by using a loading instruction to obtain a test coverage rate, wherein the test coverage rate is used as the test coverage rate of the first chip for running the actual test instruction case.
In a second aspect, the present application provides another chip verification method, including determining a control parameter; selecting a corresponding sequence of instructions in a test template based on an unused random value, the test template comprising a plurality of instructions; generating an actual test instruction case according to the selected instruction sequence and the control parameter; and when the test coverage rate obtained when the first chip runs the actual test instruction case is larger than a preset value, controlling the first chip to run the actual test instruction case for multiple times, finishing if a defect bug occurs, and otherwise, executing the step of selecting the corresponding instruction sequence based on other unused random values again.
In the method, after a control parameter is determined by a verification device or a component for verifying the chip, different actual test instruction cases are respectively obtained based on the control parameter and instruction series combinations generated by different random values, and then the chip to be verified (namely, a first chip) can be verified by using different actual test instruction cases generated based on the same control parameter and different random values, and when the test coverage rate obtained by operating one actual test instruction case on the first chip is greater than a preset value, the first chip can be continuously controlled to continuously operate the actual test instruction case for multiple times until the chip to be verified is tested to have bug. Therefore, when the chip is verified, the circular verification can be carried out without personnel participation, so that the verification efficiency and the verification accuracy can be improved.
In one possible design, a control parameter may be randomly selected first when determined; selecting a corresponding instruction sequence in a test template by using a corresponding random numerical value, and generating a simulation test instruction case based on the instruction sequence and the control parameter; and when the test coverage rate obtained when the first chip runs the simulation test instruction case is larger than a preset value, taking the selected control parameter as the determined control parameter.
Because the test coverage rate obtained after the first chip operates the instruction sequence obtained based on the corresponding random value and the instruction case generated by the control parameter is greater than the preset value, the control parameter can be determined to be a better control parameter, and the better random value is used as the control parameter for subsequently generating the actual test instruction case, so that the test accuracy can be further improved.
In one possible design, the selecting a corresponding instruction sequence in the test template based on an unused random value includes: a plurality of instruction index values are calculated based on an unused random number value, and a corresponding instruction sequence is selected in the test template based on the calculated plurality of instruction index values.
In the method, how to obtain the instruction sequence based on the random numerical value is given, and the instruction index value obtained by calculating based on the random numerical value selects the corresponding instruction sequence, so that the method for selecting the instruction is simpler and is easy to operate.
In a possible design, after obtaining that the test coverage obtained when the first chip runs the simulation test instruction case is greater than a preset value, continuing to control the first chip to run the simulation test instruction case for M times, and obtaining M test coverage respectively; and when determining that at least N test coverage rates in the M test coverage rates are larger than a preset value, determining the selected control parameter as a determined control parameter, wherein M and N are positive integers, and M > -N.
Therefore, the determined control parameters can be ensured to be more excellent, and a good basis is provided for subsequently generating an actual test instruction case with a better test effect.
In a possible design, if a bug occurs in the first chip during the test, the determined control parameter may be further stored in a control parameter set, and the control parameter set may be used to provide the control parameter when verifying the second chip.
Therefore, the verification chip proves that the selected control parameters are optimized, and the determined control parameters are stored in the control parameter set, so that the better control parameters can be continuously learned and accumulated in the control parameter set, the better control parameters can be preferentially provided when other chips (such as a second chip) are verified, the time for searching and determining the control parameters when the second chip is verified is reduced, and the verification efficiency is further improved.
In one possible design, the test coverage may be determined, but is not limited to, by at least one of:
reading a PMU (power management unit) register of a performance monitoring unit by using a system state reading register to a general register MRS (parameter switching) instruction to obtain a test coverage rate which is used as the test coverage rate of the actual test instruction case run by the first chip; or
Using MRS instruction to read special register to obtain test coverage rate as the test coverage rate of the first chip for running the actual test instruction case; or
And reading the memory of the first chip by using a loading instruction to obtain a test coverage rate, wherein the test coverage rate is used as the test coverage rate of the first chip for running the actual test instruction case.
In a third aspect, the present application further provides an apparatus having the functions of implementing the first or second aspects. The functions can be realized by hardware, and the functions can also be realized by executing corresponding software by hardware. The hardware or software includes one or more modules corresponding to the above-described functions.
In one possible design, the apparatus may include a processing unit and a storage unit in the structure, and may further include a communication unit and the like, and these units may perform the corresponding ones in the first aspect or the second aspect example. The apparatus may be constructed, for example, to include a processor and a memory coupled to the processor, the memory storing necessary program instructions and data. The memory is used for storing a computer program; the processor is configured to execute the computer program stored in the memory to perform the respective functions of the first or second aspect described above.
In a fourth aspect, the present application also provides a computer storage medium having stored thereon computer-executable instructions for causing a computer to perform the method as set forth in any one of the possible designs of the first aspect or the method as set forth in any one of the possible designs of the second aspect when invoked by the computer.
In a fifth aspect, the present application also provides a computer program product comprising instructions which, when run on an apparatus, cause the apparatus to perform the method as mentioned in any one of the possible designs of the first aspect above, or cause the apparatus to perform the method as mentioned in any one of the possible designs of the second aspect above.
In a sixth aspect, the present application further provides an apparatus, which may be a chip, connected to a memory, and configured to read and execute program instructions stored in the memory to implement the method mentioned in any one of the possible designs of the first aspect, or to implement the method mentioned in any one of the possible designs of the second aspect.
Drawings
FIG. 1 is a schematic diagram of a conventional verification framework for verifying a chip;
FIG. 2 is a schematic diagram of a verification framework for verifying a chip according to an embodiment of the present disclosure;
fig. 3 is a flowchart illustrating a method for verifying a chip according to an embodiment of the present disclosure;
FIG. 4 is a diagram illustrating a process for selecting a corresponding instruction sequence according to a random value according to an embodiment of the present disclosure;
fig. 5 is a flowchart of a complete method for verifying a chip according to an embodiment of the present disclosure;
FIG. 6 is a detailed flowchart of another method for verifying a chip according to an embodiment of the present disclosure;
FIG. 7 is a flowchart of another method for verifying a chip according to an embodiment of the present disclosure;
FIG. 8 is a schematic structural diagram of a first apparatus according to an embodiment of the present disclosure;
fig. 9 is a schematic structural diagram of a second apparatus according to an embodiment of the present application.
Detailed Description
Embodiments of the present application will be described in further detail below with reference to the accompanying drawings.
The embodiment of the application provides a chip verification method and device, which are used for solving the problems that in the prior art, personnel is required to participate when verifying whether a bug exists in a chip, the operation is complex, and the verification efficiency is low. The method and the device are based on the same inventive concept, and because the principles of solving the problems of the method and the device are similar, the implementation of the device and the method can be mutually referred, and repeated parts are not repeated.
When a research and development staff develops a new chip, all functions of the chip need to be verified, and the chip can be put into the market after verification is successful. When the functions of the chip are verified, the most critical problem is to verify whether the chip has a bug, if so, a verifier needs to analyze the bug to find out the reason of the bug, and the chip is continuously verified after the reason of the bug is solved. The verification of the chip may be to verify the "memory consistency" of the chip, whether a bug exists in the aspects of CPU interrupt, exception, page table and virtualization, branch prediction, instruction fetching, decoding, micro-operation decomposition, distribution, transmission, write-back, instruction submission, rollback and the like, or to verify all SOC systems including the CPU.
Before introducing the embodiments of the present application, a description is first defined on several key concepts related to the embodiments of the present application to facilitate better understanding of implementation processes of the embodiments of the present application.
1) The random numerical value is a numerical value randomly generated by adopting some random algorithms, can be a 64-bit hexadecimal number, and can be calculated by using a preset algorithm based on the hexadecimal number to obtain a group of numerical sequences which can be used as an instruction index value sequence; the random algorithm refers to that a random function is used, and the return value of the random function directly or indirectly influences the execution flow or the execution result of the algorithm.
2) The test template is a test instruction library which is generated by a tester according to experience in advance and used for storing an instruction set and instruction constraints, wherein the instruction set comprises at least one instruction, various instructions which are pre-programmed by the tester aiming at different chips are included in the instruction set, the different instructions can form an instruction sequence, and the instruction sequence and different control parameters for testing the chip to be verified can form a test instruction case; the instruction constraints include constraints for selecting instructions, i.e., functions for calculating instruction index values.
3) And the control parameters are used for controlling parameters used by different instructions in the instruction sequence during operation, and different test parameters can be set for the chip to be verified in order to test different test points of different chips to be verified, so that the aim of testing different test points is fulfilled.
4) And the test instruction case is used for generating an operating program which can directly act on the chip to be verified, and when the operating program is operated by the chip to be verified, if a problem exists, the bug is usually triggered. The test instruction case consists of an instruction sequence and control parameters, and the process of running the instruction case by the chip to be verified is to use the instruction in the instruction case to access the corresponding address in the chip to be verified so as to obtain the corresponding data in the chip, wherein the address is indicated by the control parameters in the instruction sequence.
5) And the test coverage rate refers to the ratio of the number of different tested functional values output by the chip to be verified after the test instruction case is run to the number of functional values expected to be required.
6) And the instruction index value is an index value calculated by using a preset algorithm according to the random value, and corresponding instructions can be indexed in the test template based on different instruction index values.
7) Plural means two or more.
8) The terms "first," "second," and the like in the description of the present application are used for descriptive purposes only and are not intended to indicate or imply relative importance nor order to be construed.
Currently, for chip verification, verification processing is usually performed based on a verification framework diagram shown in fig. 1, as shown in fig. 1, the conventional verification framework diagram includes a random instruction generator, which includes a random value generator, a test template, and an instruction generation module. The test template comprises an instruction set and instruction constraints, wherein the instruction set is predefined and comprises a plurality of instructions; some constraint conditions are stored in the instruction constraint and used for generating an instruction index value; and the instruction generating module is used for indexing an instruction from the instruction set according to an instruction index value generated by instruction constraint to finally obtain an instruction sequence. When verifying whether a chip to be verified has a problem, the random value generator is configured to randomly generate a random value, which may also be referred to as a "seed", where the "seed" may be a 64-bit hexadecimal value, the random value generator generates a plurality of instruction index values according to the "seed" and a constraint condition in an instruction constraint, then the instruction generation module selects a plurality of corresponding instructions from an instruction set according to the instruction index values to form an instruction sequence, combines the instruction sequence and a default control parameter into an instruction case, and outputs the instruction case to a target chip (i.e., the chip to be verified), the chip to be verified runs the instruction case, and then collects a test coverage when the target chip runs the instruction case by using functions such as "assertion" or "test coverage" of an electronic design automation (eda) tool, and then the collected information such as the test coverage rate is stored in a folder by a coverage rate analysis tool. Subsequent verifiers can modify or improve the instruction set in the test template according to the information such as the test coverage rate and the like stored in the file; in the process of verifying and running the instruction use case by the target chip, if the bug exists, the verification is stopped, and a verifier can analyze the bug.
It should be noted that the assertion refers to checking the unexpected situation when the instruction use case is executed, and when the unexpected situation occurs, the assertion, that is, an error is reported, and the verification is stopped.
To facilitate understanding of the prior art method of verifying a chip, the following description is given by way of example.
For example, there are 10 instructions in the instruction set in the test template, instruction a, instruction B, instruction C, instruction D, instruction E, instruction F, instruction G, instruction H, instruction I, and instruction J, and the random number generator randomly selects a "seed" to be 123, and according to the instruction constraint condition in the instruction constraint and the "seed" 123, randomly selecting instruction sequences of instruction A, instruction E and instruction F from the test template, combining the instruction A, instruction E, instruction F and default control parameters into a test instruction case, outputting the test instruction case to a target chip, operating the test instruction sequence by the target chip, the test coverage rate obtained by running the test command case on the target chip is collected by the eda tool, if the collected test coverage information is 70%, if the target chip needs to verify 10 functions, then there are 3 that are not verified, and the verifier can modify or improve the test template according to the 3 unverified functions.
In order to improve the efficiency of chip verification, the framework in fig. 1 may be modified in the scheme of this embodiment, so as to avoid artificial modification and perfection that depends on too many verification personnel, thereby aiming at improving the verification efficiency and the verification accuracy.
The verification framework implemented by the embodiment of the present application may be as shown in fig. 2, and includes an adaptive instruction generator, which includes an adaptive expert system controller, a random number generator, an instruction generation module, and a performance monitoring unit counter. The adaptive expert system controller comprises a test template and a control parameter template, wherein the test template comprises an instruction set and instruction constraints, the control parameter template comprises a control parameter set, and control parameters in the control parameter set are used for controlling parameters used by different instructions in an instruction sequence during operation; the random value generator can randomly generate seeds, the instruction constraint conditions and the seeds in the instruction constraints can generate a plurality of instruction index values, and the instruction generation module indexes a plurality of instructions in the instruction set according to the instruction index values to generate an instruction sequence; the performance monitoring unit counter can automatically count whether the test coverage rate of the chip to be verified during the operation of the instruction sequence reaches a preset value, and if the test coverage rate reaches the preset value, the performance monitoring unit counter is triggered to be increased by 1.
Based on the verification framework shown in fig. 2, an embodiment of the present application provides a method for verifying a chip, which is applicable to the adaptive instruction generator shown in fig. 2, and referring to fig. 3, a specific process of the method for verifying a chip provided in the embodiment of the present application includes:
step 300, determining a random number.
In an optional implementation manner, a random value generator in the adaptive instruction generator randomly generates a random value, based on the random value, a corresponding instruction sequence is selected from a test template in the adaptive instruction generator, after a simulation test instruction case is generated according to the instruction sequence and a default control parameter, the chip to be verified runs the simulation test instruction case, after the chip to be verified runs the simulation test instruction case, it is determined whether a test coverage rate obtained when the chip to be verified runs the simulation test instruction case is greater than a preset value, and if the test coverage rate is greater than the preset value, the random value is used as the random value determined in step 300.
For example, the default control parameter may be one control parameter in a preset set of control parameters. Specifically, the adaptive expert system controller may read the default control parameter from the chip to be verified according to the storage address of the default control parameter.
The test coverage rate of the chip to be verified after the simulation test instruction case is run can be obtained through at least one of the following three ways:
reading a PMU (performance monitor unit) register by using a MRS (Mobile to general purpose register) instruction in an adaptive expert system controller to obtain a test coverage rate;
reading a special register by using an MRS instruction in the adaptive expert system controller to obtain the test coverage rate;
and thirdly, reading the memory of the chip to be verified by using a loading instruction in the adaptive expert system controller to obtain the test coverage rate.
It should be noted that, when the test coverage is obtained by reading the PMU register with the MRS instruction, the test coverage information obtained by running the simulation test instruction case by the chip to be verified is stored in the PMU register; when the test coverage rate is obtained by reading the special register through the MRS instruction, the test coverage rate information obtained by running the simulation test instruction case by the chip to be verified is stored in the special register, and because each special register has a definite function, the test coverage rate can be obtained by reading the special register with the function of storing the test coverage rate through the MRS; when the test coverage rate is obtained by using a mode of reading the memory of the chip to be verified by using the loading instruction, the test coverage rate information obtained by the chip to be verified running the simulation test instruction case is stored in the memory of the chip to be verified.
In an alternative embodiment, the corresponding instruction sequence is selected from the test template based on a random value, a plurality of instruction index values may be first calculated based on the random value, and then the corresponding instruction sequence is selected from the test template of the adaptive instruction generator based on the plurality of instruction index values calculated.
For ease of understanding, the corresponding instruction sequence is selected based on a random value, as illustrated below.
Fig. 4 is a schematic diagram illustrating a process for selecting a corresponding instruction sequence according to a random value according to an embodiment of the present application. In fig. 4, X is a selected random number, X may be a 64-bit hexadecimal number, and a series of number sequences (Y1, Y2, Y3 …, Yn) are respectively obtained by calculation based on a preset first function Y ═ f1(X), where X is used as an initial input value of the function Y ═ f1(X) when Y1 is obtained based on X, and the last calculation result value is used as an input value of the function Y ═ f1(X) each time when Y2, Y3 …, Yn are subsequently calculated. Then, the number sequence (Y1, Y2, Y3 …. Yn) is used as an instruction index value sequence, and instructions Z that can be indexed in the test template by the respective instruction index values Y are respectively calculated based on a preset second function Z ═ f2(Y), so that the instruction sequence (Z1, Z2, Z3 …. Zn) can be indexed in the test template according to the instruction index value sequence (Y1, Y2, Y3 …. Yn).
It should be noted that a set of digit sequences is calculated based on random digits by using a preset algorithm, where the preset algorithm Y ═ f1(X) may be obtained according to instruction constraints.
In an optional implementation manner, after the performance monitoring unit counter obtains that the test coverage obtained when the chip to be verified runs the simulation test instruction case is greater than a preset value, the adaptive instruction generator may control the chip to be verified to continue running the simulation test instruction case M times, after it is determined that N test coverage are all greater than the preset value in the obtained M test coverage, the generated random value is finally used as the random value determined in the step 300, where M is greater than or equal to N. Thus, the selected random value is guaranteed to be more excellent, and can be defined as an excellent random value or an excellent seed.
For example, if the preset value is 80%, M is 5, N is 3, and after the test coverage obtained by obtaining that the chip to be verified runs a simulation test instruction case is 90%, the chip to be verified can be controlled to continue running the simulation test instruction case for 5 times, the obtained 5 test coverage is 85%, 88%, 90%, 91%, and 79%, and since 4 of the obtained 5 test coverage are greater than the preset value 80%, the random value of the instruction sequence generating the simulation test instruction case can be used as a good random value, that is, a good "seed". The good "seed" can subsequently be used as the true "seed" used in generating the actual test instruction case.
Step 301, the adaptive expert system controller selects a corresponding instruction sequence in a test template based on the random value, wherein the test template comprises a plurality of instructions.
After the random value is determined, selecting a corresponding instruction sequence in the test template based on the random value, where a process of selecting a corresponding instruction sequence in the test template based on the random value is the same as a process of selecting a corresponding instruction sequence from the test template based on the random value when determining a random value, and repeated description is omitted.
Step 302, the adaptive expert system controller repeatedly executes the following steps based on the selected instruction sequence:
traversing an unexplored control parameter in a preset control parameter set, and generating an actual test instruction case according to the selected instruction sequence and the control parameter obtained by traversal; and when the test coverage rate obtained when the actual test instruction case is operated by the chip to be verified is obtained and is greater than a preset value, controlling the chip to be verified to operate the instruction case for multiple times, ending if bug occurs, and otherwise, executing the step of traversing one control parameter which is not traversed in the preset control parameter set again.
Different control parameters in the preset control parameter set can be preset according to different functions of the chip to be verified, for example, some control parameters of the chip a to be verified can be preset for the chip a to be verified, and some control parameters preset for the chip a to be verified are stored in the preset control parameter set when the chip a to be verified is verified; the control parameters of the chip B to be verified are preset aiming at the chip B to be verified, and when the chip B to be verified is verified, the control parameters preset aiming at the chip B to be verified are stored in a preset control parameter set.
Traversing an unexplored control parameter in the preset control parameter set, namely, when an actual test instruction case is generated according to the selected instruction sequence and the control parameter each time, the control parameter is a control parameter which is not used in the preset control parameter set before the actual test instruction case is generated at this time, so that the chip to be verified is prevented from repeatedly running some same instruction cases, and time waste is avoided.
After an actual test instruction case is generated, the chip to be verified runs the actual test instruction case, and the test coverage rate obtained after the chip to be verified runs the actual test instruction case is obtained, wherein the test coverage rate obtained after the chip to be verified runs the instruction case is obtained in the same manner as the test coverage rate obtained after the chip to be verified runs the simulation test instruction case, and repeated description is omitted here.
In a possible implementation manner, when the chip to be verified runs the actual test instruction case, if a bug occurs, the random number value of the instruction sequence generating the actual test instruction case may be stored in a random number set, and the random number in the random number set may be used to provide a good random number value when verifying other target chips, so that time may be better saved for verifying other target chips.
In an optional implementation manner, if the control parameter that is not traversed cannot be traversed in the preset control parameter set, the step of determining other random values may be returned to, and then the steps 301 and 302 are repeatedly executed until the chip to be verified has a bug.
The chip verification method comprises the steps of firstly determining a random value, then selecting a corresponding instruction sequence based on the random value, traversing control parameters, generating an actual test instruction case according to the instruction sequence and the traversed control parameters, controlling the chip to be verified to operate the actual test instruction case for multiple times when the test coverage rate obtained by the chip to be verified operating the actual test instruction case is greater than a preset value, stopping verification if bugs occur, continuously traversing the control parameters if bugs do not occur, circularly verifying the chip to be verified through some preset conditions, and therefore personnel participation is not needed, the operation is simple and convenient, and the verification efficiency can be improved.
Based on the embodiment shown in fig. 3, an embodiment of the present application further provides a flowchart of a complete method for chip verification, and referring to fig. 5, the flowchart of this example may specifically include:
step 500, a random number generator randomly selects a random number X, a group of digital sequences is obtained by calculation through a preset algorithm based on the random number X, the group of digital sequences can be used as an instruction index value sequence, and then corresponding instructions are sequentially selected from a test template by using the instruction index value sequence to form an instruction sequence;
step 501, the adaptive expert system controller combines the obtained command sequence (Z1, Z2, Z3 …. Zn) with default control parameters to generate a simulation test command case, specifically, the default control parameters can be read according to the memory address of the default control parameters, then the default control parameters are combined with the obtained command sequence (Z1, Z2, Z3 …. Zn) to generate the simulation test command case, and then the target chip runs the simulation test command case;
step 502, a performance monitoring unit counter acquires the test coverage rate output by a target chip after running the simulation test instruction case;
step 503, the performance monitoring unit counter judges whether the test coverage output by the target chip after running the simulation test instruction case is larger than a preset value, if so, step 504 is executed, otherwise, the step 500 is returned, the adaptive expert system controller triggers the random instruction generator to randomly select other X values, and then the step 500-step 502 are continuously executed; it should be noted that, if the random number X selected in the step 500 is an X that has not been selected before, for example, after the step 500 to the step 502 are performed based on the selected X1 for the first time, if the step 500 is returned again, the step X2 is selected, and the step 500 to the step 502 are performed based on the X2 again.
Judging whether a simulation test instruction case is a good simulation test instruction case when the simulation test instruction case is verified for a target chip, wherein one of the judging standards is whether the test coverage rate obtained when the target chip runs the simulation test instruction case reaches a preset value, if the test coverage rate can reach the preset value, the simulation test instruction case can be shown to be a better simulation test instruction case, for example, the test coverage rate obtained after the target chip runs the simulation test instruction case is 10%, namely, the simulation test instruction case is verified to be only 10% when the target chip is verified, if a random value in the simulation test instruction case with the test coverage rate of 10% is used for generating an instruction sequence, and then the instruction sequence and the traversed control parameter are used for generating an actual test instruction case for verifying whether the chip has bugs, the verification efficiency is low, therefore, it is necessary to determine that the simulation test command case is a better simulation test command case.
Step 504, the adaptive expert system controller continues to control the target chip to run the simulation test instruction case for M times, and the performance monitoring unit counter obtains M test coverage results respectively output by the M times of running;
step 505, if N test coverage results in the M test coverage results are all greater than a preset value, executing step 506; otherwise, returning to the step 500, the self-adaptive expert system controller triggers the random instruction generator to randomly select other X values and then continues to execute the step 500 to the step 502; it should be noted that, if the random number X selected in the step 500 is an X that has not been selected before, for example, after the step 500 to the step 502 are performed based on the selected X1 for the first time, if the step 500 is returned again, the step X2 is selected, and the step 500 to the step 502 are performed based on the X2 again.
Where M > ═ N, for example, M may be 5 and N may be 3.
It should be noted that, in step 503, the adaptive expert system controller determines whether the simulation test instruction case is a better simulation test instruction case according to the state of the performance monitoring unit counter, if the performance monitoring unit counter is incremented by 1, it may be determined that the simulation test instruction case is a better simulation test instruction case, since the target chip only runs the simulation test instruction case once, in order to further determine that the simulation test instruction case is indeed a better simulation test instruction case, the target chip continues to be controlled to run the simulation test instruction case M times, and if N results in the obtained M results of the test coverage are greater than a preset value, it is determined that the simulation test instruction case is a better instruction case.
Step 506, the adaptive expert system controller triggers the random instruction generator to re-execute the operation in the step 500 according to the random number X, indexes an instruction sequence (Z1, Z2, Z3 …. Zn) in the test template, and judges whether an unretraversed control parameter can be traversed in the control parameter set, specifically, whether an unretraversed storage address can be traversed in the address set of the storage address corresponding to each control parameter, if so, step 507 is executed, otherwise, the step 500 is returned, and the adaptive expert system controller triggers the random instruction generator to randomly select other X values and then continuously executes the steps 500 to 502; it should be noted that, if the random number X selected in the step 500 is an X that has not been selected before, for example, after the step 500 to the step 502 are performed based on the selected X1 for the first time, if the step 500 is returned again, the step X2 is selected, and the step 500 to the step 502 are performed based on the X2 again.
Step 507, the adaptive expert system controller generates an actual test instruction case based on the instruction sequence (Z1, Z2, Z3 …. Zn) and the traversed control parameters;
step 508, after the adaptive expert system controller controls the target chip to run the actual test instruction case, the performance monitoring unit counter obtains the test coverage rate output by the target chip running the actual test instruction case;
509, judging whether the test coverage output by the target chip after running the actual test instruction case is greater than a preset value by the performance monitoring unit counter, if so, executing the step 510, otherwise, returning to continue executing the step 506;
step 510, the adaptive expert system controller continues to control the target chip to run the actual test instruction case for K times;
step 511, the adaptive expert system controller determines whether bug occurs in the process that the target chip runs the actual test instruction case for K times, if yes, the test is finished; otherwise, the procedure returns to step 506.
After the step 504 is executed, if N test coverage results in the M test coverage results are all greater than the preset value, the selected random number X may be stored, or a storage address corresponding to the selected random number X may be stored, so that when other chips are subsequently tested, the stored good random numbers may be preferentially selected, or good random numbers may be obtained according to the storage address of the stored good random number, thereby reducing the time spent in finding good random numbers and improving the efficiency of finding good random numbers.
Based on the verification framework shown in fig. 2, an embodiment of the present application further provides a method for verifying a chip, which is applicable to the adaptive instruction generator shown in fig. 2, and referring to fig. 6, a specific process of another method for verifying a chip provided in the embodiment of the present application includes:
step 600, determining a control parameter.
In an optional implementation manner, firstly, a self-adaptive expert system controller randomly selects a control parameter, selects a corresponding instruction sequence in a test template by using a corresponding random value, and generates a simulation test instruction case based on the instruction sequence and the control parameter; and when the test coverage rate obtained when the chip to be verified, which is obtained by the counter of the performance monitoring unit, runs the simulation test instruction case is greater than a preset value, taking the selected control parameter as the control parameter determined in the step 600.
For example, one randomly selected control parameter may be selected from one preset control parameter set, and the control parameters in the preset control parameter set may be different for different chips to be verified.
In an alternative embodiment, the corresponding instruction sequence is selected from the test template using the corresponding random value, a plurality of instruction index values may be calculated based on an unused random value, and the corresponding instruction sequence may be selected from the test template of the adaptive instruction generator based on the plurality of instruction index values calculated.
The corresponding random value may be a previously unused random value generated randomly.
The test coverage of the chip to be verified after running the simulation test instruction case is obtained in the same manner as the test coverage of the chip to be verified after running the simulation test instruction case in the method shown in fig. 3, and is not repeated here.
In an optional implementation manner, after the performance monitoring unit counter obtains that the test coverage obtained when the chip to be verified runs the simulation test instruction case is greater than a preset value, the adaptive instruction generator may control the chip to be verified to run the simulation test instruction case M times, after it is determined that N test coverage are greater than the preset value in the obtained M test coverage, the control parameter in the simulation test instruction case is finally used as the control parameter determined in the step 600, where M is greater than or equal to N. Therefore, the selected control parameter can be ensured to be more excellent and can be defined as an excellent control parameter.
Step 601, selecting a corresponding instruction sequence in a test template based on an unused random value, wherein the test template comprises a plurality of instructions.
In an alternative embodiment, a plurality of instruction index values are calculated based on an unused random value, and a corresponding instruction sequence is selected in the test template based on the plurality of instruction index values calculated.
Step 602, generating an actual test instruction case according to the selected instruction sequence and the control parameter.
Here, the purpose of generating the actual test instruction case is to enable the target chip to run the actual test instruction case to obtain the test coverage, and similarly, the manner of obtaining the test coverage is the same as the manner of obtaining the test coverage after the chip to be verified runs the simulation test instruction case in the method of fig. 3, and repeated description is omitted here.
And 603, when the performance monitoring unit counter obtains that the test coverage rate obtained when the target chip runs the actual test instruction case is greater than a preset value, the adaptive expert system controller controls the target chip to run the actual test instruction case for multiple times, if bug occurs, the operation is finished, otherwise, the step of selecting a corresponding instruction sequence based on other unused random values is executed again.
In a possible implementation manner, when the actual test instruction case is run by the chip to be verified, bug occurs, the control parameter for generating the actual test instruction case may be marked in the preset control parameter set, and the control parameter marked in the preset control parameter set may be used to provide a good control parameter when verifying other target chips, so that time may be better saved for verifying other target chips.
The other chip verification method provided above includes determining a control parameter, generating an actual test instruction case based on an unused random value and the control parameter, controlling the chip to be verified to run the actual test instruction case for multiple times after obtaining that a test coverage rate obtained by running the actual test instruction case by the chip to be verified is greater than a preset value, stopping verification if a bug occurs, and continuing to use other unused random values to select a corresponding instruction sequence if the bug does not occur.
Based on the embodiment shown in fig. 6, the embodiment of the present application further provides another complete method flowchart for chip verification, and referring to fig. 7, the flowchart of this example may specifically include:
step 700, the adaptive expert system controller randomly selects a control parameter P from a preset control parameter set; specifically, a storage address may be randomly selected from an address set of storage addresses corresponding to each control parameter, and the control parameter P may be obtained according to the selected storage address;
701, a random number generator randomly selects a random number X, a group of digital sequences are obtained by calculation through a preset algorithm based on the random number X, the group of digital sequences can be used as an instruction index value sequence, and then an instruction generation module sequentially selects corresponding instructions from a test template by using the instruction index value sequence to form an instruction sequence;
step 702, the adaptive expert system controller combines the obtained command sequence (Z1, Z2, Z3 …. Zn) with the control parameter P to generate a simulation test command case, and then controls the target chip to run the simulation test command case;
703, acquiring the test coverage rate output by the target chip after the target chip runs the simulation test instruction case by using a performance monitoring unit counter;
step 704, the performance monitoring unit counter judges whether the test coverage output after the target chip runs the simulation test instruction case is larger than a preset value, if so, step 705 is executed, otherwise, steps 710-711-702 are executed, and the simulation test instruction case is generated by using the random value X generated in step 700 and other randomly selected control parameters P; it should be noted that the random control parameter P selected in step 711 is P that has not been selected previously, such as P1 selected in step 701, and if step 710 is executed, P2 is selected.
Step 705, the adaptive expert system controller continues to make the target chip run the simulation test instruction case M times, and the performance monitoring unit counter obtains M test coverage results respectively output by the M times of running.
Step 706, if N test coverage results in the M test coverage results are all larger than a preset value, determining the control parameter P randomly selected before as a good control parameter, and fixing the control parameter P, then executing step 707; otherwise, executing steps 710-711-702, and generating a simulation test instruction case by using the random value X generated in the step 700 and other randomly selected control parameters P; it should be noted that the random control parameter P selected in step 711 is P that has not been selected previously, such as P1 selected in step 701, and if step 710 is executed, P2 is selected.
Where M > ═ N, for example, M may be 5 and N may be 3.
Step 707, the random number generator re-executes the operation in step 700, that is, re-randomly selects other numbers X that have not been selected before, where it should be noted that, the random number X selected in step 700 is the X that has not been selected before, such as X1 selected in step 700 for the first time, if step 700 is executed again, X2 is selected, a new command sequence (Z1, Z2, Z3 …. Zn)' is re-indexed in the test template based on X2, and the re-indexed new command sequence is combined with the determined good control parameter P to generate an actual test command case, and the target chip is controlled to obtain a test coverage after running the actual test command case, and whether the test coverage is greater than a preset value is determined, if yes, step 708 is executed; otherwise, returning to the step 701, and continuing to execute the steps 702-706 after randomly selecting other random numerical values X; it should be noted that the other random value X selected in the step 701 is X that has not been selected previously, such as X1 is selected for the first time, and if the step 701 is returned again, X2 is selected.
Step 708, the adaptive expert system controller continues to control the target chip to run the actual test instruction case for K times;
709, the self-adaptive expert system controller determines whether bug occurs in the process that the target chip runs the actual test instruction case for K times, if yes, the test is finished; otherwise, returning to continue executing step 700;
step 710, the instruction generating module generates an instruction use case by using the random number X in step 701;
step 711, the adaptive expert system controller randomly generates unused control parameters P.
After the step 706 is executed, if N test coverage results in the M test coverage results are all greater than the preset value, the control parameter P may be marked in the preset control parameter set, or the storage address corresponding to the control parameter P in the address set corresponding to the parameter set is marked, so that when other chips are subsequently verified, the control parameter with the mark in the preset control parameter set may be preferentially selected, or the storage address with the mark in the address set corresponding to the preset parameter set may be preferentially selected, and the good control parameter is obtained according to the selected storage address, thereby reducing the time spent in searching the good control parameter and improving the efficiency of searching the good control parameter.
The embodiment of the application provides two methods for verifying the chip, and the two methods are used for circularly verifying the chip by setting some preset conditions, so that personnel are not required to participate, and the verification efficiency is improved.
Based on the above embodiments, the present application further provides an apparatus for implementing the method for verifying a chip as shown in fig. 3 or fig. 5. Referring to fig. 8, the apparatus 800 includes: a processing unit 801 and a storage unit 802, wherein the storage unit 802 is used for storing program codes; the processing unit 801, when the program code is executed by the processing unit 801, enables the processing unit 801 to perform steps 300 to 302 shown in fig. 3, or to perform steps 500 to 511 shown in fig. 5, or enables the processing unit 801 to perform steps 600 to 603 shown in fig. 6, or to perform steps 700 to 711 shown in fig. 7.
By adopting the device provided by the embodiment of the application, a random numerical value is determined, a corresponding instruction sequence is selected based on the random numerical value, and the following steps are repeatedly executed based on the instruction sequence: firstly traversing an unretraversed control parameter, and then generating an actual test instruction case according to a selected instruction sequence and the control parameter obtained by traversal; and when the test coverage rate obtained when the chip runs the actual test instruction case is larger than a preset value, the chip runs the actual test instruction case for multiple times, if a defect bug occurs, the operation is finished, and otherwise, the step of traversing one control parameter which is not traversed in the preset control parameter set is executed again. Therefore, when the chip is verified, the verification can be carried out circularly according to the preset condition without personnel participation, the operation is simple, and the verification efficiency can be improved.
Or, by using the apparatus provided in the embodiment of the present application, a control parameter is determined, corresponding instruction sequences are respectively selected based on different random values, and the following steps are repeatedly performed based on each selected instruction sequence: generating an actual test instruction case by the determined control parameters; and when the test coverage rate obtained when the chip runs the actual test instruction case is larger than a preset value, the chip runs the actual test instruction case for multiple times, if a defect bug occurs, the test is finished, otherwise, the step of generating the actual test instruction case by using the combination of the instruction sequence determined by other random values and the control parameter is executed again. Therefore, when the chip is verified, the verification can be carried out circularly according to the preset condition without personnel participation, the operation is simple, and the verification efficiency can be improved.
It should be noted that the division of the unit in the embodiment of the present application is schematic, and is only a logic function division, and there may be another division manner in actual implementation. The functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application may be substantially implemented or contributed by the prior art, or all or part of the technical solution may be embodied in a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, a network device, or the like) or a processor (processor) to execute all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a read-only memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.
Based on the above embodiments, the present application further provides an apparatus, as shown in fig. 9, the apparatus 900 includes: the processor 901, optionally, further includes a memory 902, where the processor 901 may be a Central Processing Unit (CPU), a Network Processor (NP), or a combination of a CPU and an NP. The processor 901 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a Programmable Logic Device (PLD), or a combination thereof. The PLD may be a Complex Programmable Logic Device (CPLD), a field-programmable gate array (FPGA), a General Array Logic (GAL), or any combination thereof.
The processor 901 and the memory 902 are connected to each other. Optionally, the processor 901 and the memory 902 are connected to each other through a bus 903; the bus 903 may be a Peripheral Component Interconnect (PCI) bus, an Extended Industry Standard Architecture (EISA) bus, or the like. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, only one thick line is shown in FIG. 9, but this does not indicate only one bus or one type of bus.
The apparatus shown in fig. 9 may be the adaptive instruction generator in fig. 2, or may be a control unit or control unit in the adaptive instruction generator in fig. 2. The processing unit 801 in fig. 8 described above may be implemented based on the processor 901 herein, and the storage unit 802 may be implemented based on the memory 902 herein. For the detailed operation and execution principle of the processor 901 and the memory 902, please refer to the detailed description of the above method embodiments, which is not repeated here.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
It will be apparent to those skilled in the art that various changes and modifications may be made in the embodiments of the present application without departing from the scope of the embodiments of the present application. Thus, if such modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to encompass such modifications and variations.

Claims (28)

  1. A method of chip verification, comprising:
    determining a random value;
    selecting a corresponding instruction sequence in a test template based on the random value, wherein the test template comprises a plurality of instructions;
    repeatedly executing the following steps based on the instruction sequence:
    traversing an unexplored control parameter in a preset control parameter set, and generating an actual test instruction case according to the selected instruction sequence and the control parameter obtained by traversal;
    and when the test coverage rate obtained when the first chip runs the actual test instruction case is larger than a preset value, controlling the first chip to run the actual test instruction case for multiple times, ending if a defect bug occurs, and otherwise, executing the step of traversing one control parameter which is not traversed in the preset control parameter set again.
  2. The method of claim 1, wherein said determining a random number value comprises:
    randomly generating a random number value;
    selecting a corresponding instruction sequence in the test template based on the random numerical value, and generating a simulation test instruction case according to the selected instruction sequence and default control parameters;
    and when the test coverage rate obtained when the first chip runs the simulation test instruction case is larger than a preset value, taking the generated random value as a determined random value.
  3. The method of claim 1 or 2, wherein selecting the corresponding instruction in the test template based on the random value to obtain an instruction sequence comprises:
    and calculating a plurality of instruction index values based on the random numerical value, and selecting a corresponding instruction sequence in the test template based on the plurality of instruction index values obtained by calculation.
  4. The method according to any one of claims 1 to 3, wherein after the step of traversing one of the non-traversed control parameters in the predetermined set of control parameters is executed again, the method further comprises:
    and if the control parameters which are not traversed cannot be traversed in the control parameter set, returning to execute the step of determining other random values.
  5. The method of claim 2, wherein the generating the random number is preceded by determining a random number, further comprising:
    when the test coverage rate obtained when the first chip runs the simulation test instruction case is larger than a preset value, controlling the first chip to run the simulation test instruction case for M times to respectively obtain M test coverage rates;
    determining that at least N test coverage rates in the M test coverage rates are larger than a preset value; and M and N are both positive integers, and M > -N.
  6. The method of claim 1 or 2, further comprising:
    and if the bug occurs, storing the determined random number value into a random number set, wherein the random number set is used for providing the random number value when the second chip is verified.
  7. The method of claim 2, wherein the default control parameter is one of the preset set of control parameters.
  8. The method of any of claims 1 to 7, wherein the test coverage is determined by at least one of:
    reading a PMU (power management unit) register of a performance monitoring unit by using a system state reading register to a general register MRS (parameter switching) instruction to obtain a test coverage rate which is used as the test coverage rate of the actual test instruction case run by the first chip; or
    Using MRS instruction to read special register to obtain test coverage rate as the test coverage rate of the first chip for running the actual test instruction case; or
    And reading the memory of the first chip by using a loading instruction to obtain a test coverage rate, wherein the test coverage rate is used as the test coverage rate of the first chip for running the actual test instruction case.
  9. A method of chip verification, comprising:
    determining a control parameter;
    selecting a corresponding sequence of instructions in a test template based on an unused random value, the test template comprising a plurality of instructions;
    generating an actual test instruction case according to the selected instruction sequence and the control parameter;
    and when the test coverage rate obtained when the first chip runs the actual test instruction case is larger than a preset value, controlling the first chip to run the actual test instruction case for multiple times, finishing if the Bug occurs, or else, executing the step of selecting the corresponding instruction sequence based on other unused random values again.
  10. The method of claim 9, wherein said determining a control parameter comprises:
    randomly selecting a control parameter;
    selecting a corresponding instruction sequence in a test template by using a corresponding random numerical value, and generating a simulation test instruction case based on the instruction sequence and the control parameter;
    and when the test coverage rate obtained when the first chip runs the simulation test instruction case is larger than a preset value, taking the selected control parameter as a determined control parameter.
  11. The method of claim 9 or 10, wherein selecting the corresponding sequence of instructions in the test template based on an unused random value comprises:
    a plurality of instruction index values are calculated based on an unused random number value, and a corresponding instruction sequence is selected in the test template based on the calculated plurality of instruction index values.
  12. The method of claim 10, wherein the selecting the control parameter as the determined one control parameter is preceded by:
    when the test coverage rate obtained when the first chip runs the simulation test instruction case is larger than a preset value, controlling the first chip to run the simulation test instruction case for M times, and obtaining M test coverage rates respectively;
    determining that at least N test coverage rates in the M test coverage rates are larger than a preset value; and M and N are both positive integers, and M > -N.
  13. The method of claim 9 or 10, further comprising:
    and if the bug occurs, storing the determined control parameter into a control parameter set, wherein the control parameter set is used for providing the control parameter when the second chip is verified.
  14. The method of any of claims 9 to 13, wherein the test coverage is determined by at least one of:
    reading a PMU (power management unit) register of a performance monitoring unit by using a system state reading register to a general register MRS (parameter switching) instruction to obtain a test coverage rate which is used as the test coverage rate of the actual test instruction case run by the first chip; or
    Using MRS instruction to read special register to obtain test coverage rate as the test coverage rate of the first chip for running the actual test instruction case; or
    And reading the memory of the first chip by using a loading instruction to obtain a test coverage rate, wherein the test coverage rate is used as the test coverage rate of the first chip for running the actual test instruction case.
  15. An apparatus, comprising: a processor and a memory, the processor coupled with the memory;
    the memory for storing a computer program;
    the processor, for executing the computer program stored in the memory, to cause the apparatus to perform determining a random value; selecting a corresponding instruction sequence in a test template based on the random value, wherein the test template comprises a plurality of instructions; repeatedly executing the following steps based on the instruction sequence: traversing an unexplored control parameter in a preset control parameter set, and generating an actual test instruction case according to the selected instruction sequence and the control parameter obtained by traversal; and when the test coverage rate obtained when the first chip runs the actual test instruction case is larger than a preset value, controlling the first chip to run the actual test instruction case for multiple times, ending if the first chip has a defect bug, and otherwise, executing the step of traversing one control parameter which is not traversed in the preset control parameter set again.
  16. The apparatus as claimed in claim 15, wherein said processor, when determining a random number, is further configured to:
    randomly generating a random number value;
    selecting a corresponding instruction sequence in the test template based on the random numerical value, and generating a simulation test instruction case according to the selected instruction sequence and default control parameters;
    and when the test coverage rate obtained when the first chip runs the simulation test instruction case is larger than a preset value, taking the generated random value as a determined random value.
  17. The apparatus of claim 15 or 16, wherein the processor, when selecting the corresponding sequence of instructions in the test template based on the random value, is specifically configured to:
    and calculating a plurality of instruction index values based on the random numerical value, and selecting a corresponding instruction sequence in the test template based on the plurality of instruction index values obtained by calculation.
  18. The apparatus of any of claims 15 to 17, wherein the processor is further configured to:
    and if the control parameters which are not traversed cannot be traversed in the control parameter set, returning to execute the step of determining other random values.
  19. The apparatus of claim 16, wherein the processor is further configured to:
    before the generated random value is used as a determined random value, after the test coverage rate obtained when the first chip runs the simulation test instruction case is larger than a preset value, controlling the first chip to run the simulation test instruction case for M times, and respectively obtaining M test coverage rates;
    determining that at least N test coverage rates in the M test coverage rates are larger than a preset value; and M and N are both positive integers, and M > -N.
  20. The apparatus of claim 15 or 16, wherein the processor is further configured to:
    and if the first chip has bug, storing the determined random number value into a random number set, wherein the random number set is used for providing the random number value when a second chip is verified.
  21. The apparatus of any of claims 15 to 20, wherein the test coverage is determined by at least one of:
    the processor reads a PMU (power management unit) register of a performance monitoring unit by using a system status register to a general register MRS (parameter switching) instruction to obtain a test coverage rate which is used as the test coverage rate of the actual test instruction case run by the first chip; or
    The processor reads a special register by using an MRS instruction to obtain a test coverage rate which is used as the test coverage rate of the first chip for running the actual test instruction case; or
    And the processor reads the memory of the first chip by using the loading instruction to obtain the test coverage rate which is used as the test coverage rate of the first chip for running the actual test instruction case.
  22. An apparatus, comprising: a processor and a memory, the processor coupled with the memory;
    the memory for storing a computer program;
    the processor, for executing the computer program stored in the memory, to cause the apparatus to perform determining a control parameter; selecting a corresponding sequence of instructions in a test template based on an unused random value, the test template comprising a plurality of instructions; generating an actual test instruction case according to the selected instruction sequence and the control parameter; and when the test coverage rate obtained when the first chip runs the actual test instruction case is larger than a preset value, controlling the first chip to run the actual test instruction case for multiple times, finishing if the first chip has a defect Bug, and otherwise, executing the step of selecting the corresponding instruction sequence based on other unused random values again.
  23. The apparatus as claimed in claim 22, wherein said processor, when determining a control parameter, is specifically configured to:
    randomly selecting a control parameter;
    selecting a corresponding instruction sequence in a test template by using a corresponding random numerical value, and generating a simulation test instruction case based on the instruction sequence and the control parameter; and when the test coverage rate obtained when the first chip runs the simulation test instruction case is larger than a preset value, taking the selected control parameter as a determined control parameter.
  24. The apparatus of claim 22 or 23, wherein the processor, when selecting the corresponding sequence of instructions in the test template based on an unused random value, is specifically configured to:
    a plurality of instruction index values are calculated based on an unused random number value, and a corresponding instruction sequence is selected in the test template based on the calculated plurality of instruction index values.
  25. The apparatus of claim 23, wherein the processor is further configured to:
    before the selected control parameter is used as a determined control parameter, after the test coverage rate obtained when the first chip runs the simulation test instruction case is larger than a preset value, the first chip is controlled to run the simulation test instruction case for M times, and M test coverage rates are obtained respectively;
    determining that at least N test coverage rates in the M test coverage rates are larger than a preset value; and M and N are both positive integers, and M > -N.
  26. The apparatus of claim 24 or 25, wherein the processor is further configured to:
    and if the first chip has bug, storing the determined control parameters into a control parameter set, wherein the control parameter set is used for providing control parameters when a second chip is verified.
  27. The apparatus of any of claims 22 to 26, wherein the test coverage is determined by at least one of:
    the processor reads a PMU (power management unit) register of a performance monitoring unit by using a system status register to a general register MRS (parameter switching) instruction to obtain a test coverage rate which is used as the test coverage rate of the actual test instruction case run by the first chip; or
    The processor reads a special register by using an MRS instruction to obtain a test coverage rate which is used as the test coverage rate of the first chip for running the actual test instruction case; or
    And the processor reads the memory of the first chip by using the loading instruction to obtain the test coverage rate which is used as the test coverage rate of the first chip for running the actual test instruction case.
  28. A computer-readable storage medium comprising a program or instructions for performing the method of any one of claims 1-14 when the program or instructions are run on a computer.
CN201880099920.XA 2018-12-06 2018-12-06 Chip verification method and device Pending CN113168364A (en)

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CN115576821A (en) * 2022-10-20 2023-01-06 沐曦科技(成都)有限公司 Verification method, verification device, electronic equipment and storage medium
CN116362057A (en) * 2023-05-08 2023-06-30 上海奎芯集成电路设计有限公司 Random verification method, device, electronic equipment and storage medium
WO2023216077A1 (en) * 2022-05-09 2023-11-16 华为技术有限公司 Attestation method, apparatus and system

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CN102902834B (en) * 2011-07-29 2015-12-09 炬芯（珠海）科技有限公司 A kind of verification method of SOC and system
US9310433B2 (en) * 2014-04-18 2016-04-12 Breker Verification Systems Testing SOC with portable scenario models and at different levels
CN107704384A (en) * 2017-09-14 2018-02-16 郑州云海信息技术有限公司 A kind of convergent method and system of speed-up chip functional verification

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WO2023216077A1 (en) * 2022-05-09 2023-11-16 华为技术有限公司 Attestation method, apparatus and system
CN115308518A (en) * 2022-10-10 2022-11-08 杭州三海电子有限公司 Method and system for determining parameter measurement sequence of burn-in circuit
CN115308518B (en) * 2022-10-10 2022-12-23 杭州三海电子有限公司 Parameter measurement sequence determination method and system for burn-in circuit
CN115576821A (en) * 2022-10-20 2023-01-06 沐曦科技(成都)有限公司 Verification method, verification device, electronic equipment and storage medium
CN115576821B (en) * 2022-10-20 2024-01-19 沐曦科技(成都)有限公司 Verification method and device, electronic equipment and storage medium
CN116362057A (en) * 2023-05-08 2023-06-30 上海奎芯集成电路设计有限公司 Random verification method, device, electronic equipment and storage medium
CN116362057B (en) * 2023-05-08 2023-11-10 上海奎芯集成电路设计有限公司 Random verification method, device, electronic equipment and storage medium

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