CN109144806B - Function verification method and device for register transmission stage circuit - Google Patents
Function verification method and device for register transmission stage circuit Download PDFInfo
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- CN109144806B CN109144806B CN201710464293.2A CN201710464293A CN109144806B CN 109144806 B CN109144806 B CN 109144806B CN 201710464293 A CN201710464293 A CN 201710464293A CN 109144806 B CN109144806 B CN 109144806B
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- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
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- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
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Abstract
The embodiment of the invention provides a method and a device for verifying the function of a register transmission stage circuit, which are used for solving the problem that the function verification of the register transmission stage circuit in the prior art takes too long time. The method comprises the following steps: the register transmission stage circuit is divided into a plurality of computing units and a control unit used for controlling the cooperation of the computing units to realize the circuit function; testing the computing unit; testing the control unit; and when each computing unit and the control unit are determined to pass the test, determining that the function verification of the register transmission stage circuit passes.
Description
Technical Field
The invention relates to the technical field of digital circuits, in particular to a method and a device for verifying functions of a register transmission stage circuit.
Background
With the rapid development of digital circuit technology, the application range of the digital circuit technology is wider and wider, the chip scale becomes larger and the function becomes more and more complex, so that the work of circuit verification becomes more important and harder. And if the error cannot be found in time in the verification stage, huge loss can be caused.
For the hardware design of Register Transfer Level (RTL), a general verification method is performed from the following aspects: full traversal verification, full random verification, critical parameter (kernel) verification, and mass copying verification. Generally, if a design can be verified in a full coverage mode, the reliability of the design is very high, but for the design of an algorithm class, because the number of input parameters is very large, the range value of each parameter is large, if the design is verified in a full coverage mode, the amount of test cases (cases) required by simulation is huge, the time is possibly long, and the project duration is a great test.
The existing verification process is shown in fig. 1, and full traversal test, directional traversal test and full random test are three main test processes. The full traversal test refers to traversal test of all input conditions of each function, the directional traversal test refers to test under special input conditions, and the full random test refers to test under completely random parameter conditions. Wherein a full traversal test takes too long due to all input cases to traverse each function. How to reduce the time required for verification while ensuring the verification effect has not been proposed in the prior art.
Disclosure of Invention
The embodiment of the invention provides a method and a device for verifying the function of a register transmission stage circuit, which are used for solving the problem that the function verification of the current RTL circuit consumes too long time.
The embodiment of the invention provides the following specific scheme:
in a first aspect, a method for verifying a function of a register transfer stage circuit includes:
the register transmission stage circuit is divided into a plurality of computing units and a control unit used for controlling the cooperation of the computing units to realize the circuit function;
testing the computing unit;
testing the control unit;
and when each computing unit and the control unit are determined to pass the test, determining that the function verification of the register transmission stage circuit passes.
With reference to the first aspect, in a first possible implementation manner, the testing the computing unit includes:
determining each input parameter corresponding to the computing unit;
determining all value combinations of the input parameters corresponding to the computing unit;
and sequentially testing the computing units according to all value combinations of the input parameters corresponding to the computing units.
With reference to the first possible implementation manner of the first aspect, in a second possible implementation manner, sequentially testing the computing unit according to all value combinations of the input parameters corresponding to the computing unit includes:
setting a probe unit with the same calculation function as the calculation unit;
connecting the input end of the probe unit with the input end of the calculation unit;
all value combinations of all input parameters corresponding to the computing unit are sequentially input, and the output result of the probe unit and the output result of the computing unit are compared;
and when all the output results are determined to be the same, determining that the computing unit passes the test.
With reference to the first aspect, in a third possible implementation manner, the testing the control unit includes:
sequentially determining each input parameter corresponding to the current function aiming at each function of the register transmission stage circuit;
and selecting value combinations of all input parameters corresponding to the current function, and testing the control unit.
With reference to the third possible implementation manner of the first aspect, in a fourth possible implementation manner, selecting a value combination of each input parameter corresponding to the current function, and testing the control unit includes:
respectively taking values of each input parameter corresponding to the current function according to a preset step length;
and sequentially testing the control units according to the combination of the output parameters and the result of the preset step length value.
In a second aspect, a function verification apparatus for a register transfer stage circuit includes:
the dividing module is used for dividing the register transmission stage circuit into a plurality of computing units and a control unit for controlling the cooperation of the computing units to realize the circuit function;
the computing unit testing module is used for testing the computing unit;
the control unit testing module is used for testing the control unit;
and the result determining module is used for determining that the functional verification of the register transmission stage circuit is passed when each computing unit and the control unit are determined to pass the test.
With reference to the second aspect, in a first possible implementation manner, the computing unit testing module includes:
the first parameter identification module is used for determining each input parameter corresponding to the calculation unit;
a value determining module, configured to determine all value combinations of the input parameters corresponding to the computing unit;
and the first parameter testing module is used for sequentially testing the computing units according to all value combinations of the input parameters corresponding to the computing units.
With reference to the first possible implementation manner of the second aspect, in a second possible implementation manner, the first parameter testing module is specifically configured to:
setting a probe unit with the same calculation function as the calculation unit;
connecting the input end of the probe unit with the input end of the calculation unit;
all value combinations of all input parameters corresponding to the computing unit are sequentially input, and the output result of the probe unit and the output result of the computing unit are compared;
and when all the output results are determined to be the same, determining that the computing unit passes the test.
With reference to the second aspect, in a third possible implementation manner, the control unit testing module includes:
the second parameter identification module is used for determining each input parameter corresponding to the current function for each function of the register transmission stage circuit in sequence;
and the second parameter testing module is used for selecting the value combination of each input parameter corresponding to the current function and testing the control unit.
With reference to the third possible implementation manner of the second aspect, in a fourth possible implementation manner, the second parameter testing module is specifically configured to:
respectively taking values of each input parameter corresponding to the current function according to a preset step length;
and sequentially testing the control units according to the combination of the output parameters and the result of the preset step length value.
The register transmission stage circuit is divided into a plurality of computing units and a control unit for controlling the cooperation of the computing units to realize the circuit function, the computing units are tested, the control unit is tested, and when each computing unit and the control unit are determined to pass the test, the function verification of the register transmission stage circuit is determined to pass; compared with the prior art that the circuit function is directly tested, the method and the device greatly reduce the number of input parameters of each test, thereby reducing the number of combinations among the parameters, further reducing the number of test cases, simultaneously testing the control unit and ensuring that each computing unit can normally work in a cooperative manner, and finally achieving the effect of testing the circuit function at a higher speed on the whole.
Drawings
FIG. 1 is a schematic flow chart of an RTL verification test in the prior art according to an embodiment of the present invention;
FIG. 2 is a flow chart of a method for verifying the function of a register transfer stage circuit according to an embodiment of the present invention;
FIG. 3 is a flowchart illustrating a method for testing a computing unit according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of an RTL circuit according to an embodiment of the present invention;
FIG. 5 is a flow chart illustrating an RTL verification test according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of an RTL circuit for verifying a computing unit according to an embodiment of the present invention;
FIG. 7 is a schematic structural diagram of a functional verification apparatus for a register transfer stage circuit according to an embodiment of the present invention;
FIG. 8 is a schematic diagram of another structure of a functional verification apparatus for a register transfer stage circuit according to an embodiment of the present invention;
fig. 9 is a schematic structural diagram of an apparatus for determining a maximum similarity region in a graph according to an embodiment of the present invention.
Detailed Description
The embodiment of the invention provides a method and a device for verifying the function of a register transmission stage circuit, which solve the problem that the function verification of the register transmission stage circuit in the prior art takes too long time.
Referring to fig. 2, a method for verifying a function of a register transfer stage circuit according to an embodiment of the present invention includes:
s210, dividing the register transmission stage circuit into a plurality of computing units and a control unit for controlling the cooperation of the computing units to realize the circuit function.
The division mode can be automatically divided according to a preset program, and the division result can also be manually input.
The computing unit is characterized in that each group of fixed input corresponds to fixed output, and test cases corresponding to input and output parameters are set; the control unit involves coordination of a plurality of computing units, and therefore verification needs to be performed at a functional level, including verification of input and final output results involving the plurality of computing units.
And S220, testing the computing unit.
Preferably, S220 includes: determining each input parameter corresponding to the computing unit; determining all value combinations of the input parameters corresponding to the computing unit; and sequentially testing the computing units according to all value combinations of the input parameters corresponding to the computing units. I.e. a full traversal test of the computational unit.
Specifically, as shown in fig. 3, the method for testing the computing unit includes:
s310, setting a probe unit with the same calculation function as the calculation unit;
s320, connecting the input end of the probe unit with the input end of the calculation unit;
s330, sequentially inputting all value combinations of all input parameters corresponding to the computing unit, and comparing the output result of the probe unit with the output result of the computing unit;
and S340, when all the output results are determined to be the same, determining that the computing unit passes the test.
The probe unit generates input excitation and correct output results, and the output results generated by the calculation unit are compared with the output results generated by the probe unit, so that whether the calculation unit has problems or not can be judged.
After the test is finished and before the hardware is realized, the probe unit code is deleted.
And S230, testing the control unit.
Preferably, the control unit is tested, including: sequentially determining each input parameter corresponding to the current function aiming at each function of the register transmission stage circuit; and selecting value combinations of all input parameters corresponding to the current function, and testing the control unit.
Specifically, selecting a value combination of each input parameter corresponding to the current function, and testing the control unit includes: respectively taking values of each input parameter corresponding to the current function according to a preset step length; and sequentially testing the control units according to the combination of the output parameters and the result of the preset step length value. The control unit tests mainly to verify whether the control logic is normal, partial values are verified for each group of parameters, and each possible value condition under the same control logic is not required to be covered, so that the test quantity can be reduced and the test efficiency can be improved according to a certain step length value.
And S240, when each computing unit and the control unit are determined to pass the test, determining that the function verification of the register transmission stage circuit passes.
The concept of the invention will be described in detail below with reference to specific embodiments.
Fig. 4 is a schematic diagram of a circuit under test, which is mainly used for calculation, and includes 8 calculation units (calc _ unit) and an associated control unit (control _ unit), and the input parameters of the module include 8 (par _0, par _1, par _2 … … par _7), and each parameter has a bit width of 10 bits.
For circuit function, full traversal verification is a relatively full-face verification means, and as long as all conditions of input parameters are traversed, it can be ensured that the function is not performedAnd (5) problems are solved. In the embodiment of the present invention, there are 8 input parameters, and the bit width of each parameter is 10 bits, so if the full traversal coverage test is performed, the required maximum case number is 280Assuming that one case can run out in 3 seconds, it takes 256 days to run out of these cases, which is obviously too long.
In addition, for the verification of the control unit, whether the verification is complete or not can be seen by analyzing the coverage rate, but for the calculation unit, whether the conditional coverage rate, toggle coverage rate, line coverage rate and the like reach 100% or not, whether the calculation logic of the design is completely verified or not cannot be completely represented, and therefore, the purpose of completely verifying cannot be achieved by only seeing the coverage rate.
Based on the above reasons, the embodiment of the invention respectively verifies each kind of computing unit, and if all the computing units are traversed once, the verification of the logic of the control unit is combined with the pseudo-full traversal test, which is equivalent to traversing the function of the whole circuit.
Referring to fig. 5, the verification method provided by the embodiment of the present invention includes the following test procedures:
1. performing pseudo full traversal test;
the pseudo-full traversal test is used for testing the control logic of the function, and can be increased by a certain step length to be taken as each parameter value, and the step length can be set to be 2. Compared with the real full traversal, the number of pseudo full traversal cases is equivalent to the previous 1/(2)8). The pseudo-full traversal design is a test item with the largest cases, so that the selection of the step length directly influences the test time length, the maximum value, the minimum value and some intermediate values of the corresponding parameters of the functions can be traversed only by the pseudo-full traversal design, and the step length can be set to be larger, so that the design becomes the pseudo-full traversal design.
2. Probe traversal test
Firstly, the calculation logic in the design is decomposed into a plurality of small calculation units, and it should be noted that each calculation unit is independent in calculation logic, and the input parameters of each calculation unit cannot be too much, and are generally 5-6. After the decomposition, corresponding full traversal test logic is designed for each computing unit, namely, the computing units are probe units, and the probe units are put into a test platform (TestBench). The full traversal test is completed by directly applying the excitation generated by the probe unit to the computing unit and simultaneously comparing the output result of the computing unit with the output result of the probe unit. The probe units can be simultaneously opened, and because the input parameters of each probe unit are only 5-6, the number of cases respectively traversed in a full mode is small, and the time is short. Fig. 6 shows a schematic diagram of a probe test mode. Because the compute units are computationally independent, their combination represents the entire computational logic, and the combination of the traversals of the compute units is also equivalent to the traversals of the entire computational path.
3. Directional traversing design;
the directional test includes a corner test, a special function point test, etc., and the directional traversal is not the midpoint of the present invention, and is not described herein.
4. Designing fully randomly;
the full random test means that all parameters are random, a large number of simulations are performed, and full random traversal is not the key point of the invention and is not repeated herein.
After all the 4 tests pass, the coverage collection step is entered. If the coverage rate does not meet the requirement, the reason needs to be analyzed, and meanwhile, cases are filled up until the coverage rate requirement is met, and the test is finished.
Referring to fig. 7, an embodiment of the present invention provides a function verification apparatus for a register transfer stage circuit, including:
a dividing module 710, configured to divide the register transmission stage circuit into a plurality of computing units, and a control unit configured to control the computing units to cooperate to implement a circuit function;
a computing unit testing module 720, configured to test the computing unit;
a control unit testing module 730, configured to test the control unit;
a result determination module 740 for determining that the functional verification of the register transfer stage circuit passed when each compute unit and control unit are determined to have passed the test.
Referring to fig. 8, the calculation unit test module 720 includes:
a first parameter identification module 721, configured to determine each input parameter corresponding to the computing unit;
a value determining module 722, configured to determine all value combinations of the input parameters corresponding to the computing unit;
the first parameter testing module 723 is configured to sequentially test the computing units according to all value combinations of the input parameters corresponding to the computing units.
Preferably, the first parameter testing module 723 is specifically configured to:
setting a probe unit with the same calculation function as the calculation unit;
connecting the input end of the probe unit with the input end of the calculation unit;
all value combinations of all input parameters corresponding to the computing unit are sequentially input, and the output result of the probe unit and the output result of the computing unit are compared;
and when all the output results are determined to be the same, determining that the computing unit passes the test.
Referring to fig. 8, the control unit test module 730 includes:
a second parameter identification module 731, configured to determine, for each function of the register transfer stage circuit in sequence, each input parameter corresponding to the current function;
the second parameter testing module 732 is configured to select a value combination of each input parameter corresponding to the current function, and test the control unit.
Preferably, the second parameter testing module 732 is specifically configured to:
respectively taking values of each input parameter corresponding to the current function according to a preset step length;
and sequentially testing the control units according to the combination of the output parameters and the result of the preset step length value.
In summary, the present invention achieves the purpose of equivalently traversing the entire data path by decomposing the entire data path into small computing units and performing traversal tests on these computing units, and achieves the effect of reducing the simulation case and not reducing the simulation reliability by combining the verification on the control unit.
As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, optical storage, and the like) having computer-usable program code embodied therein.
The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (2)
1. A method for verifying the functionality of a register transfer stage circuit, comprising:
the register transmission stage circuit is divided into a plurality of computing units and a control unit used for controlling the cooperation of the computing units to realize the circuit function;
testing the computing unit;
testing the control unit;
when each computing unit and each control unit are determined to pass the test, determining that the function verification of the register transmission level circuit passes;
testing the computing unit, including:
determining each input parameter corresponding to the computing unit;
determining all value combinations of the input parameters corresponding to the computing unit;
sequentially testing the computing units according to all value combinations of the input parameters corresponding to the computing units;
and sequentially testing the computing units according to all value combinations of the input parameters corresponding to the computing units, wherein the step of testing the computing units comprises the following steps:
setting a probe unit with the same calculation function as the calculation unit;
connecting the input end of the probe unit with the input end of the calculation unit;
all value combinations of all input parameters corresponding to the computing unit are sequentially input, and the output result of the probe unit and the output result of the computing unit are compared;
when all the output results are determined to be the same, determining that the computing unit passes the test;
testing the control unit, including:
sequentially determining each input parameter corresponding to the current function aiming at each function of the register transmission stage circuit;
selecting value combinations of all input parameters corresponding to the current function, and testing the control unit;
selecting value combinations of all input parameters corresponding to the current functions, and testing the control unit, wherein the value combinations comprise:
respectively taking values of each input parameter corresponding to the current function according to a preset step length;
and sequentially testing the control units according to the combination of the output parameters and the result of the preset step length value.
2. A functional verification apparatus for a register transfer stage circuit, comprising:
the dividing module is used for dividing the register transmission stage circuit into a plurality of computing units and a control unit for controlling the cooperation of the computing units to realize the circuit function;
the computing unit testing module is used for testing the computing unit;
the control unit testing module is used for testing the control unit;
the result determining module is used for determining that the function verification of the register transmission stage circuit passes when each computing unit and each control unit are determined to pass the test;
the computational unit test module includes:
the first parameter identification module is used for determining each input parameter corresponding to the calculation unit;
a value determining module, configured to determine all value combinations of the input parameters corresponding to the computing unit;
the first parameter testing module is used for sequentially testing the computing units according to all value combinations of all input parameters corresponding to the computing units;
the first parameter testing module is specifically configured to:
setting a probe unit with the same calculation function as the calculation unit;
connecting the input end of the probe unit with the input end of the calculation unit;
all value combinations of all input parameters corresponding to the computing unit are sequentially input, and the output result of the probe unit and the output result of the computing unit are compared;
when all the output results are determined to be the same, determining that the computing unit passes the test;
the control unit test module includes:
the second parameter identification module is used for determining each input parameter corresponding to the current function for each function of the register transmission stage circuit in sequence;
the second parameter testing module is used for selecting value combinations of all input parameters corresponding to the current function and testing the control unit;
the second parameter testing module is specifically configured to:
respectively taking values of each input parameter corresponding to the current function according to a preset step length;
and sequentially testing the control units according to the combination of the output parameters and the result of the preset step length value.
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| US8429580B2 (en) * | 2008-11-07 | 2013-04-23 | Apple Inc. | Method for preparing for and formally verifying a modified integrated circuit design |
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