CN109933948B - Form verification method, device, form verification platform and readable storage medium - Google Patents
Form verification method, device, form verification platform and readable storage medium Download PDFInfo
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Abstract
The invention discloses a form verification method, a form verification device, a form verification platform and a readable storage medium, wherein the form verification method comprises the following steps: acquiring a source operand to be verified which is input into a model to be tested; judging whether the source operand to be verified belongs to a necessary verification source operand; if the source operand to be verified does not belong to the necessary verification source operand, determining that the to-be-verified source operand is used as input, and the to-be-tested model is equal to the output result of the reference model; if the source operand to be verified belongs to the necessary verification source operand, a form verification tool is started, the verification source operand to be verified is taken as input, and verification is carried out according to the output result of the model to be verified and the output result of the reference model. Before the form verification tool is started to verify whether the output results of the model to be tested and the reference model are equal, whether the source operand to be verified belongs to the source operand to be verified of the model to be tested is judged, and the risk of the space explosion problem of the form verification method is reduced.
Description
Technical Field
The present invention relates to the field of integrated circuits, and in particular, to a form verification method, apparatus, electronic device, and readable storage medium.
Background
The form verification is to mathematically and completely prove or verify whether the implementation scheme of the circuit actually realizes the function described by the circuit design, and the idea is to firstly establish a priority state model (model to be tested) of the system to be tested, then use an algorithm to exhaust the states in the model to be tested to judge whether the model can realize the expected function, in practical application, generally compare the output results of all the state spaces of the model to be tested with the corresponding output results of a reference model (model capable of correctly realizing the expected function of the model to be tested) to judge whether the model to be tested can realize the expected function, so the form verification is a completeness verification method capable of traversing the whole state space of the design. Compared with the traditional simulation verification method, the formal verification method can quickly find out counterexample positioning errors without building a complex verification platform and building a large number of test vectors, and particularly when random test in the simulation verification is difficult to cover boundary conditions, the method is more effective, so that the formal verification is widely paid attention to in recent years. However, since formal verification is based on an exhaustive search verification of the state space, there is always a risk of space explosion problems when using formal verification methods to verify devices under test (Device Under Test, DUT). Particularly, with the continuous development of multiple cores and multiple threads, the problem of space explosion is increasingly more and more generated when a form verification method is used due to the fact that the instruction is provided with the higher operation efficiency of a processor but the higher complexity of an operation state space, such as a decomposition instruction, a convertible clock period instruction and the like, and the problem is gradually unavoidable.
Disclosure of Invention
In view of the above, the embodiments of the present invention provide a form verification method, apparatus, electronic device, and readable storage medium, so as to solve the problem that the existing form verification method has a large risk of space explosion.
According to a first aspect, an embodiment of the present invention provides a form verification method, including the steps of: acquiring a source operand to be verified which is input into a model to be tested; judging whether the source operand to be verified belongs to a necessary verification source operand, wherein the necessary verification source operand is data which can be input into all the source operands of the model to be tested and is necessary to be verified; if the source operand to be verified does not belong to the necessary verification source operand, determining that the output result of the model to be verified is equal to the output result of the source operand to be verified input into the reference model when the source operand to be verified is input into the model to be verified; the reference model is a model for correctly realizing the function of the model to be tested; if the source operand to be verified belongs to the necessary verification source operand, a form verification tool is started, the source operand to be verified is used as input to be respectively input into the model to be verified and the reference model, and verification is carried out according to the output result of the model to be verified and the output result of the reference model.
By respectively inputting the source operand to be verified as input into the model to be verified and the reference model before the form verification tool is started and verifying according to the output result of the model to be verified and the output result of the reference model, whether the source operand to be verified belongs to data which are required to be verified in all the source operands capable of being input into the model to be verified is judged, when the source operand to be verified does not belong to the source operand which is required to be verified, the form verification tool is directly determined (the verification result is directly obtained), and when the source operand to be verified is input into the model to be verified, the output result of the model to be verified is equal to the output result of the source operand to be verified which is input into the reference model, so that the calculated amount (part of state space is directly used for obtaining the verification result) in the process of traversing all the state spaces of the model to be verified is reduced, the risk of space explosion problem of the form verification method in the embodiment of the invention is reduced while the completeness of verification is ensured, and the problem of large risk of space explosion problem of the existing form verification method is solved.
With reference to the first aspect, in a first implementation manner of the first aspect, the model to be tested is a model for performing addition or subtraction operation, and each inputtable source operand includes a first source operand and a second source operand; the necessary verification of the source operands means that both the first source operand and the second source operand are normalized numbers.
With reference to the first aspect, in a second implementation manner of the first aspect, the model to be tested is a model for performing addition or subtraction operation, and each inputtable source operand includes a first floating point source operand and a second floating point source operand; it is necessary to verify that the exponent bits of the second floating point source operand are greater than or equal to 1/2 of the exponent bits of the first floating point source operand.
With reference to the first aspect or the first implementation manner or the second implementation manner of the first aspect, in a third implementation manner of the first aspect, a form verification tool is started, a source operand to be verified is input into a model to be tested and a reference model as input, and verification is performed according to an output result of the model to be tested and an output result of the reference model, including: starting a form verification tool to verify whether the output result of the model to be tested is the same as the output result of the reference model or not when each inputtable source operand is respectively input into the model to be tested and the reference model; and if the output result of the model to be tested is the same as the output result of the reference model, outputting a verification result of the equivalence of the model to be tested and the reference model.
With reference to the third implementation manner of the first aspect, in a fourth implementation manner of the first aspect, the form verification method further includes the following steps: if the output result of the model to be tested is different from the output result of the reference model, judging whether the form verification tool has errors or not; if the form verification tool has errors, re-verifying all the input source operands after debugging; and if the form verification tool has no error, outputting a verification result of which the model to be tested is not equivalent to the reference model.
According to a second aspect, an embodiment of the present invention provides a form verification apparatus, including: the data acquisition module is used for acquiring a source operand to be verified, which is input into the model to be tested; the data judging module is used for judging whether the source operand to be verified belongs to a necessary verification source operand, wherein the necessary verification source operand is data which can be input into all the source operands of the model to be tested and is necessary to be verified; the result determining module is used for determining that when the source operand to be verified is input into the model to be verified, the output result of the model to be verified is equal to the output result of the source operand to be verified input into the reference model; the reference model is a model for correctly realizing the function of the model to be tested; the result verification module is used for starting the form verification tool, taking a source operand to be verified as input to be respectively input into the model to be tested and the reference model, and verifying according to the output result of the model to be tested and the output result of the reference model.
With reference to the second aspect, in a first implementation manner of the second aspect, the model to be tested is a model for performing an addition or subtraction operation, each inputtable source operand includes a first source operand and a second source operand, and the necessary verification of the source operand refers to that the first source operand and the second source operand are normalized numbers.
With reference to the second aspect, in a second implementation manner of the second aspect, the model to be tested is a model for performing addition or subtraction operation, and each inputtable source operand includes a first floating point source operand and a second floating point source operand; it is necessary to verify that the exponent bits of the first floating point source operand are less than 1/2 of the exponent bits of the second floating point source operand.
According to a third aspect, an embodiment of the present invention provides a formal verification platform, including: the system comprises a memory and a processor, wherein the memory and the processor are in communication connection, the memory stores computer instructions, and the processor executes the computer instructions, so as to execute the form verification method in the first aspect or any implementation manner of the first aspect.
According to a fourth aspect, an embodiment of the present invention provides a computer-readable storage medium storing computer instructions for causing a computer to perform the form verification method of the first aspect or any implementation manner of the first aspect.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of a method of formal verification method according to an embodiment of the present invention;
FIG. 2 is a flowchart of a specific method of step S104 in FIG. 1;
FIG. 3 is a flowchart of another method of formal verification analysis method according to an embodiment of the present invention;
FIG. 4a is a schematic diagram of a scenario of floating point arithmetic;
FIG. 4b is a schematic diagram of another scenario of floating point arithmetic;
FIG. 5 is a schematic block diagram of a form verification apparatus according to an embodiment of the present invention;
fig. 6 is a schematic hardware structure of an electronic device according to an embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In the description of the present invention, it should be noted that the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
Example 1
The form verification method provided by the embodiment of the invention is applied to the form verification platform used in circuit design verification, and the form verification platform can simulate verification environments of the reference model and the model to be tested, so that the reference model and the environment to be tested can normally operate, and the instruction corresponding to the form verification method in the embodiment of the invention is executed to verify whether the model to be tested realizes the expected function. Specifically, the model to be tested in the embodiment of the present invention refers to a register conversion level circuit (Register Transfer Level, RTL) model, that is, an abstract model for describing the circuit operation of a design by using a hardware description language (Verilog or VHDL), and the reference model refers to a model which is built by using a high-level language (such as a script language or C language) and can ensure that the expected function of the designed circuit can be correctly implemented.
Fig. 1 shows a flowchart of a formal verification method according to an embodiment of the invention, as shown in fig. 1, the method may include the following steps:
s101: and obtaining a source operand to be verified which is input into the model to be tested. Here, the source operand to be verified is any one data of all the inputtable source operands of the model to be tested.
S102: and judging whether the source operand to be verified belongs to the necessary verification source operand. Here, the verification source operand is necessary to verify that the source operand is data that must be verified in all the inputtable source operands that can be input into the model to be tested, specifically, by summarizing the characteristics of the function that the model to be tested expects to implement and the output result of the model to be tested when all the possible input source operands are summarized as inputs, all the possible input source operands are categorized to obtain the necessary verification source operand. Here, if the source operand to be verified does not belong to the necessary verification source operand, step S103 is performed; if the source operand to be verified belongs to the necessary verification source operand, step S104 is performed.
Specifically, taking the function expected to be implemented by the model to be tested as implementing addition (or subtraction) operation, each inputtable source operand includes a first source operand and a second source operand as examples, when the input first source operand and the second source operand are normalized numbers, specific operation is needed, and when the input first source operand or the input second source operand are denormalized numbers or special numbers (such as positive infinity, non-number and the like), the output result of the model to be tested is error reporting information; meanwhile, the reference model is a model which correctly realizes the function of the model to be tested, so that the condition of the reference model is the same as that of the model to be tested; therefore, when the first source operand or the second source operand in the inputtable source operands is a denormalized number or a special number other than the normalized number, it can be directly determined that the output result of the model to be tested is equal to the output result of the reference model when the inputtable source operand is taken as an input, that is, the inputtable source operand classification that both the first source operand and the second source operand are normalized numbers can be divided into necessary verification source operands.
Still taking the function expected to be implemented by the model to be tested as an example to implement an addition (or subtraction) operation, when the first source operand and the second source operand included in the inputtable source operand are normalized numbers, the necessary verification source operands may be further categorized.
Specifically, when the normalized number is operated by the computer, the normalized number is generally converted into a floating point number, and in order to ensure the precision of the operation result, the precision of the calculation result is generally consistent with the precision of the source operand, so when the first floating point source operand is far greater than the second floating point source operand, the range of the value of the result obtained after superposition of the two source operands is greater than the range of the precision required by the instruction, the Least Significant Bit (LSB) of the calculation result needs to be fully rounded (rounded) operation, the precision of the calculation result at the moment is basically the same as that of the first floating point source operand, and particularly when the exponent bit of the second floating point source operand is less than 1/2 of the exponent bit of the first floating point source operand, the second floating point source operand has no influence on the calculation result basically, and the first floating point source operand can be directly used as the calculation result without inputting the first floating point source operand and the second floating point source operand into the model to be measured for calculation; meanwhile, the reference model is a model which correctly realizes the function of the model to be tested, so that the condition of the reference model is the same as that of the model to be tested; therefore, when the exponent bit of the second floating point source operand in the inputtable source operand is smaller than 1/2 of the exponent bit of the first floating point source operand, the output result of the model to be tested when the inputtable source operand is input can be directly determined to be equal to the output result of the reference model, namely the inputtable source operand classification when the exponent bit of the second source operand is larger than or equal to 1/2 of the exponent bit of the first floating point source operand can be divided into necessary verification source operands.
S103: when the source operand to be verified is determined to be input into the model to be verified, the output result of the model to be verified is equal to the output result of the source operand to be verified input into the reference model. The reference model is here a model that correctly implements the function of the model to be measured.
Here, in the above example, if it is necessary to verify that the source operand is a normalized number, when the first source operand or the second source operand in the source operand to be verified is a non-normalized number or a special number, it is determined that the output result of the model to be verified is equal to the output result of the source operand to be verified input to the reference model when the source operand to be verified is input to the model to be tested; if it is necessary to verify that the exponent bits of the source operand are the inputtable source operand when the exponent bits of the second source operand are greater than or equal to 1/2 of the exponent bits of the first floating point source operand, when the exponent bits of the second floating point source operand are less than 1/2 of the exponent bits of the first floating point source operand, it is determined that the output result of the model to be verified is equal to the output result of the input of the source operand to be verified to the reference model when the source operand to be verified is input to the model to be verified.
It should be noted that, the source operand to be verified does not belong to the source operand to be verified, which does not mean that the source operand to be verified does not need to be verified, but means that the source operation data to be verified does not need to be input into the model to be tested and the reference model to be calculated to obtain the output result and then verified, so that the verification conclusion (different from the source operand to be verified) can be directly obtained, that is, the execution content of the step is still a part of the form verification.
S104: and starting a form verification tool, respectively inputting a source operand to be verified as input into the model to be tested and the reference model, and verifying according to the output result of the model to be tested and the output result of the reference model.
The form verification tool is used for providing the running environments of the to-be-tested model and the reference model so that the to-be-verified source operand can normally run to output a calculation result when the to-be-verified source operand is input into the to-be-tested model and the reference model respectively, and meanwhile, the form verification tool is also used for verifying whether the output result of the to-be-tested model is equal to the data result of the reference model. The specific configuration mode, function and function statement of the form verification tool belong to the prior art, and are not repeated here.
Here, when the output result of the model to be measured is equal to the output result of the reference model, outputting a verification result that the model to be measured is equivalent to the reference model; when the output result of the model to be tested is unequal to the output result of the reference model, outputting a verification result of errors of a form verification tool or inequivalence of the model to be tested and the reference model. In a specific application scenario, when the output result of the model to be tested is unequal to the output result of the reference model, the form verification tool can be further debug, and finally, the verification result of the error of the form verification tool is obtained, or the verification result of the inequivalence of the reference model and the reference model is obtained.
According to the form verification method provided by the embodiment of the invention, before the form verification tool is started to verify whether the source operand to be verified is used as input to input the model to be verified and the reference model to be verified respectively, whether the source operand to be verified belongs to data which are required to be verified in all the source operands capable of being input to the model to be verified is judged, and when the source operand to be verified does not belong to the source operand which is required to be verified, the form verification tool is directly determined (the verification result is not started, and the verification result is directly obtained), when the source operand to be verified is input to the model to be verified, the output result of the model to be verified is equal to the output result of the source operand to be verified which is input to the reference model to be verified, so that the calculation amount (part of the state space is directly used for obtaining the verification result) in the process of traversing all the state spaces of the model to be verified is reduced, the risk of space explosion problem in the form verification method provided by the embodiment of the invention is reduced while the completeness of verification is ensured, and the problem of the space explosion problem in the existing form verification method is solved.
As an alternative implementation of the embodiment of the present invention, as shown in fig. 2, step S104 may include the following steps:
s201: and starting a form verification tool to verify whether the output result of the model to be tested is the same as the output result of the reference model or not when each input source operand is respectively input into the model to be tested and the reference model. Here, if the output result of the model to be measured is the same as the output result of the reference model, step S202 is performed; if the output result of the model to be measured is different from the output result of the reference model, step S203 is performed.
S202: and outputting a verification result of equivalence of the model to be tested and the reference model.
S203: it is determined whether the formal verification tool has an error. Here, if the form verification tool has an error, step S204 is performed; if the formal verification tool is not in error, step S205 is performed.
S204: and re-verifying all the input source operands after debugging. Here, steps S101 to S104 (S201 to S205 included in step S104) are re-executed after the debug until the form verification result that the model to be tested is equivalent or not equivalent to the reference model is output.
S205: and outputting a verification result of inequivalence between the model to be tested and the reference model.
Fig. 3 is a flowchart of a form verification method according to another embodiment of the present invention, taking a model to be tested as a model for performing addition or subtraction operation, and taking an example that each inputtable source operand includes a first floating point source operand and a second floating point source operand, the form verification method according to the embodiment of the present invention is described, as shown in fig. 3, and the method may include the following steps:
s301: and obtaining a source operand to be verified which is input into the model to be tested. Here, the source operand to be verified is any one data of all the inputtable source operands of the model to be tested.
S302: it is determined whether an exponent of a second floating point source operand in the source operands to be validated is greater than or equal to 1/2 of an exponent of the first floating point source operand. Here, if the exponent of the second floating point source operand is less than 1/2 of the exponent of the first floating point source operand, step S303 is performed; if the exponent of the second floating point source operand is greater than or equal to 1/2 of the exponent of the first floating point source operand, step S304 is performed.
S303: when the source operand to be verified is determined to be input into the model to be verified, the output result of the model to be verified is equal to the output result of the source operand to be verified input into the reference model. The reference model is here a model that correctly implements the function of the model to be measured.
In this case, the computer generally converts the normalized number into a floating point number when calculating the normalized number, and in order to ensure the accuracy of the calculation result, the accuracy of the calculation result is generally consistent with the accuracy of the source operands, so, as shown in fig. 4a, when one floating point number src1 is far greater than the second floating point number src2, that is, when there is a gap (gap) between two source operands, the value range of the result (result) after stacking the two floating points is greater than the accuracy value range required by the instruction, then the Least Significant Bit (LSB) of the result (result) needs to be fully rounded (round) at this time, and the accuracy of the result is basically identical to that of src1, especially when the index bit of src2 is less than 1/2 of the index bit of src1, the calculation result is not affected basically, and thus, when the index of the second source operand in the source operands to be verified is less than 1/2 of the first source operands, and the floating point operands to be verified are input and output and the model to be verified respectively, and the model to be verified are input and output, and the model to be verified, and the model to be input and the model are input and the model to be input.
S304: and starting a form verification tool to verify whether the output result of the model to be tested is the same as the output result of the reference model or not when each input source operand is respectively input into the model to be tested and the reference model. Here, if the output result of the model to be measured is the same as the output result of the reference model, step S305 is performed; if the output result of the model to be measured is different from the output result of the reference model, step S306 is performed.
Here, when the range after the superposition of the two floating point number value ranges is smaller than or equal to the result, or when there is overlap (overlap) between the value range of src1 and src2 as shown in fig. 4b, calculation and verification according to the normal calculation method are required, therefore, when the exponent of the second floating point source operand is greater than or equal to 1/2 of the exponent of the first floating point source operand, a form verification tool is required to be started, and when the source operand to be verified is verified as input to the model to be tested and the reference model respectively, whether the output result of the model to be tested is the same as the output result of the reference model is verified.
S305: and outputting a verification result of equivalence of the model to be tested and the reference model.
S306: it is determined whether the formal verification tool has an error. Here, if the form verification tool has an error, step S307 is performed; if the formal verification tool is not in error, step S308 is performed.
S307: and re-verifying all the input source operands after debugging. Here, step S301 to step S307 are re-performed after the debug until the equivalent or non-equivalent form verification result is output.
S308: and outputting a verification result of inequivalence between the model to be tested and the reference model.
In the embodiment of the invention, on the premise that the model to be tested is to execute addition or subtraction operation of a computer foundation and the inputtable source operand of the model to be tested belongs to a normalized number (comprising a first floating point source operand and a second floating point source operand), whether the inputtable source operand belongs to a necessary verification source operand is further judged, so that the calculated amount in the process of traversing all state spaces of the model to be tested can be further reduced, the verification completeness is ensured, and the risk of space explosion problem in the form verification method of the embodiment of the invention is reduced.
Example 2
Fig. 5 shows a functional block diagram of a form verification device according to an embodiment of the invention, which can be used to implement the form verification method according to embodiment 1 or any alternative embodiment thereof. As shown in fig. 5, the apparatus includes: a data acquisition module 10, a data judgment module 20, a result determination module 30 and a result verification module 40.
The data acquisition module 10 is used for acquiring a source operand to be verified, which is input into the model to be tested.
The data determining module 20 is configured to determine whether the source operand to be verified belongs to a necessary verification source operand, where the necessary verification source operand is data that can be input into all the source operands of the model to be verified and must be verified. Here, if the source operand to be verified does not belong to the necessary verification source operand, the result determination module 30 is executed; if the source operand to be verified belongs to the necessary verification source operand, the result verification module 40 is executed.
The result determining module 30 is configured to determine that, when the source operand to be verified is input to the model to be verified, an output result of the model to be verified is equal to an output result of the source operand to be verified input to the reference model. The reference model is here a model that correctly implements the function of the model to be measured.
The result verification module 40 is used for starting a form verification tool, inputting a source operand to be verified as input into the model to be tested and the reference model respectively, and verifying according to the output result of the model to be tested and the output result of the reference model.
According to the form verification device provided by the embodiment of the invention, before the form verification tool is started to verify whether the source operand to be verified is used as input to the model to be verified and the reference model to be verified are respectively input, whether the source operand to be verified belongs to data which are required to be verified in all the source operands capable of being input to the model to be verified is judged, and when the source operand to be verified does not belong to the source operand to be verified, the form verification tool is directly determined (the verification result is directly obtained) and the source operand to be verified is input to the model to be verified, the output result of the model to be verified is equal to the output result of the source operand to be verified which is input to the reference model to be verified, so that the calculation amount (part of the state space is directly used for obtaining the verification result) in the process of traversing all the state spaces of the model to be verified is reduced, the risk of space explosion problem of the form verification method in the embodiment of the invention is reduced while the completeness of verification is ensured, and the problem of large risk of space explosion problem of the existing form verification method is solved.
As an alternative implementation manner of the embodiment of the present invention, the model to be tested is a model for performing addition or subtraction operation, each inputtable source operand includes a first source operand and a second source operand, and the necessary verification of the source operands means that the first source operand and the second source operand are normalized numbers.
As an optional implementation manner of the embodiment of the present invention, the model to be tested is a model for performing addition or subtraction operation, and each inputtable source operand includes a first floating point source operand and a second floating point source operand; it is necessary to verify that the exponent bits of the first floating point source operand are less than 1/2 of the exponent bits of the second floating point source operand.
The embodiment of the present invention further provides an electronic device, as shown in fig. 6, which may include a processor 61 and a memory 62, where the processor 61 and the memory 62 may be connected by a bus or other means, and in fig. 6, the connection is exemplified by a bus.
The processor 61 may be a central processing unit (Central Processing Unit, CPU). Processor 61 may also be other general purpose processors, digital signal processors (Digital Signal Processor, DSP), application specific integrated circuits (Application Specific Integrated Circuit, ASIC), field programmable gate arrays (Field-Programmable Gate Array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or a combination of the above.
The memory 62 is used as a non-transitory computer readable storage medium for storing non-transitory software programs, non-transitory computer executable programs, and modules, such as program instructions/modules (e.g., the data acquisition module 10, the data determination module 20, the result determination module 30, and the result verification module 40 in fig. 5) corresponding to the form verification method in the embodiment of the present invention. The processor 61 executes various functional applications of the processor and data processing, i.e., implements the form verification method in the above-described method embodiments, by running non-transitory software programs, instructions, and modules stored in the memory 62.
Memory 62 may include a storage program area that may store an operating system, at least one application program required for functionality, and a storage data area; the storage data area may store data created by the processor 61, etc. In addition, the memory 62 may include high-speed random access memory, and may also include non-transitory memory, such as at least one magnetic disk storage device, flash memory device, or other non-transitory solid state storage device. In some embodiments, memory 62 may optionally include memory located remotely from processor 61, which may be connected to processor 61 via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The one or more modules are stored in the memory 62 and when executed by the processor 61 perform the formal verification method in the embodiment shown in fig. 1-4 b.
The specific details of the electronic device may be understood correspondingly with reference to the corresponding related descriptions and effects in the embodiments shown in fig. 1 to 4b, which are not repeated here.
It will be appreciated by those skilled in the art that implementing all or part of the above-described embodiment method may be implemented by a computer program to instruct related hardware, where the program may be stored in a computer readable storage medium, and the program may include the above-described embodiment method when executed. Wherein the storage medium may be a magnetic Disk, an optical Disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a Flash Memory (Flash Memory), a Hard Disk (HDD), or a Solid State Drive (SSD); the storage medium may also comprise a combination of memories of the kind described above.
It is apparent that the above examples are given by way of illustration only and are not limiting of the embodiments. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. While still being apparent from variations or modifications that may be made by those skilled in the art are within the scope of the invention.
Claims (8)
1. A form verification method, comprising the steps of:
acquiring a source operand to be verified which is input into a model to be tested; each of the inputtable source operands includes a first floating point source operand and a second floating point source operand; the necessary verification source operand means that the exponent bits of the second floating point source operand are greater than or equal to 1/2 of the exponent bits of the first floating point source operand;
judging whether the source operand to be verified belongs to a necessary verification source operand, wherein the necessary verification source operand is data which can be input into all the source operands of the model to be verified and is necessary to be verified; the determining whether the source operand to be verified belongs to a necessary verification source operand includes: judging whether the exponent of the second floating point source operand in the source operand to be verified is greater than or equal to 1/2 of the exponent of the first floating point source operand;
if the source operand to be verified does not belong to the necessary verification source operand, determining that the output result of the model to be verified is equal to the output result of the source operand to be verified input into the reference model when the source operand to be verified is input into the model to be verified; the reference model is a model for correctly realizing the function of the model to be tested; the source operand to be verified not belonging to the necessary verification source operand includes: the exponent of the second floating point source operand in the source operand to be verified is less than 1/2 of the exponent of the first floating point source operand;
if the source operand to be verified belongs to the necessary verification source operand, starting a form verification tool, respectively inputting the source operand to be verified as input into a model to be verified and a reference model, and verifying according to an output result of the model to be verified and an output result of the reference model; the starting form verification tool takes the source operand to be verified as input to be respectively input into a model to be tested and a reference model, and performs verification according to the output result of the model to be tested and the output result of the reference model, and the starting form verification tool comprises the following steps: starting a form verification tool, and judging whether the output result of the model to be tested is the same as the output result of the reference model or not when each input source operand is respectively input into the model to be tested and the reference model; if the output result of the model to be tested is the same as the output result of the reference model, outputting a verification result of the equivalent of the model to be tested and the reference model; if the output result of the model to be tested is different from the output result of the reference model, judging whether the form verification tool has errors or not; if the form verification tool has errors, re-verifying all the input source operands after debugging; and if the form verification tool has no error, outputting a verification result of which the model to be tested is not equivalent to the reference model.
2. The formal verification method of claim 1, wherein the model to be tested is a model that performs an addition or a subtraction operation, and each of the inputtable source operands comprises a first source operand and a second source operand; the necessary verification of the source operands means that the first source operand and the second source operand are both normalized numbers.
3. The formal verification method of claim 1, wherein the model to be tested is a model that performs an addition or subtraction operation.
4. A form verification apparatus, comprising:
the data acquisition module is used for acquiring a source operand to be verified, which is input into the model to be tested; each of the inputtable source operands includes a first floating point source operand and a second floating point source operand; the necessary verification source operand means that the exponent bits of the second floating point source operand are greater than or equal to 1/2 of the exponent bits of the first floating point source operand;
the data judging module is used for judging whether the source operand to be verified belongs to a necessary verification source operand, wherein the necessary verification source operand is data which can be input into all the source operands of the model to be tested and is necessary to be verified; the determining whether the source operand to be verified belongs to a necessary verification source operand includes: judging whether the exponent of the second floating point source operand in the source operand to be verified is greater than or equal to 1/2 of the exponent of the first floating point source operand;
the result determining module is used for determining that when the source operand to be verified is input into the model to be verified, the output result of the model to be verified is equal to the output result of the source operand to be verified input into the reference model; the reference model is a model for correctly realizing the function of the model to be tested; the source operand to be verified not belonging to the necessary verification source operand includes: the exponent of the second floating point source operand in the source operand to be verified is less than 1/2 of the exponent of the first floating point source operand;
the result verification module is used for starting a form verification tool, taking the source operand to be verified as input to be respectively input into a model to be tested and a reference model, and verifying according to the output result of the model to be tested and the output result of the reference model; the starting form verification tool takes the source operand to be verified as input to be respectively input into a model to be tested and a reference model, and performs verification according to the output result of the model to be tested and the output result of the reference model, and the starting form verification tool comprises the following steps: starting a form verification tool, and judging whether the output result of the model to be tested is the same as the output result of the reference model or not when each input source operand is respectively input into the model to be tested and the reference model; if the output result of the model to be tested is the same as the output result of the reference model, outputting a verification result of the equivalent of the model to be tested and the reference model; if the output result of the model to be tested is different from the output result of the reference model, judging whether the form verification tool has errors or not; if the form verification tool has errors, re-verifying all the input source operands after debugging; and if the form verification tool has no error, outputting a verification result of which the model to be tested is not equivalent to the reference model.
5. The formal verification device of claim 4, wherein the model to be tested is a model for performing an addition or a subtraction operation, each of the inputtable source operands comprises a first source operand and a second source operand, and the necessary verification source operands are normalized numbers.
6. The formal verification device of claim 4, wherein the model to be tested is a model for performing an addition or a subtraction operation, and each of the inputtable source operands comprises a first floating point source operand and a second floating point source operand; the necessary verification source operand means that exponent bits of the second floating point source operand are greater than or equal to 1/2 of exponent bits of the first floating point source operand.
7. A formal verification platform, comprising: a memory and a processor in communication with each other, the memory having stored therein computer instructions, the processor executing the computer instructions to perform the formal verification method of any of claims 1-3.
8. A computer-readable storage medium storing computer instructions for causing the computer to perform the formal verification method of any one of claims 1-3.
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| CN101840367A (en) * | 2009-12-23 | 2010-09-22 | 上海高性能集成电路设计中心 | Device for verifying floating point unit of microprocessor |
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