CN109933948A - A kind of Formal Verification, device, formal verification platform and readable storage medium storing program for executing - Google Patents
A kind of Formal Verification, device, formal verification platform and readable storage medium storing program for executing Download PDFInfo
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Abstract
The invention discloses a kind of Formal Verification, device, formal verification platform and readable storage medium storing program for executing, which includes the following steps: to obtain the source operand to be verified for inputting model to be measured；Judge whether source operand to be verified belongs to necessary verifying source operand；If source operand to be verified is not belonging to necessary verifying source operand, it is determined that using source operand to be verified as when input, model to be measured is equal with the output result of reference model；If source operand to be verified belongs to necessary verifying source operand, start formal verification tool, source operand to be verified will be verified as input, verified according to the output result of the output result of model to be measured and reference model.By before whether the output result that enabling formal verification tool verifies model and reference model to be measured is equal, judge source operand to be verified whether belong to model to be measured have to verifying source operand, reduce the risk that Space Explosion problem occurs in Formal Verification.
Description
Technical field
The present invention relates to technical field of integrated circuits more particularly to a kind of Formal Verification, device, electronic equipment and
Readable storage medium storing program for executing.
Background technique
Formal verification, refers to whether the implementation for mathematically imperfectly proving or verifying circuit realizes circuit really
Described function is designed, thought is first to establish the priority status model of examining system (model to be measured), then poor with algorithm
State to the greatest extent in model to be measured judges whether it can be realized expectation function, in practical application, generally by by model to be measured
The output result of all state spaces is corresponding with reference model (model that can correctly realize the expectation function of model to be measured)
Output result is compared, and judges whether model to be measured can be realized expectation function, and therefore, formal verification is that one kind can traverse
Design the completeness verification method of entire state space.Compared with traditional simulation verification method, formalization verification method is not necessarily to
It builds complicated verification platform and constructs a large amount of test vector, it will be able to rapidly find out counter-example positioning mistake, especially work as mould
When random test is difficult to cover border condition in quasi- verifying, this method is more proved effective, and therefore, formal verification is in recent years by industry
Extensive concern.It but is therefore shape, is being used based on the exhaustive search verifying to state space just because of formal verification
When formula verification method device under test (Device Under Test, DUT) is verified, always exists and Space Explosion occur and ask
The risk of topic.In particular with the continuous development of multicore, multithreading, disassembly instruction and convertible clock cycle instructions etc. can
The it is proposed of processor operation efficiency but the higher instruction of operation state space complexity is improved, when use form verification method
The problem of risk for Space Explosion problem occur is increasing, and being increasingly becoming one can not avoid.
Summary of the invention
In view of this, the embodiment of the invention provides a kind of Formal Verification, device, electronic equipment and readable storage mediums
Matter, to solve the problems, such as that the larger problem of risk of Space Explosion occurs in existing Formal Verification.
According in a first aspect, including the following steps: to obtain input the embodiment of the invention provides a kind of Formal Verification
The source operand to be verified of model to be measured；Judge whether source operand to be verified belongs to necessary verifying source operand, necessity verifying
Source operand is that can input all of model to be measured to input in source operand, it is necessary to the data of verifying；If source to be verified
Operand is not belonging to necessary verifying source operand, it is determined that when source operand to be verified is inputted model to be measured, model to be measured
It is equal with by the source operand to be verified input output result of reference model to export result；Reference model is positive shows mould to be measured really
The model of the function of type；If source operand to be verified belongs to necessary verifying source operand, start formal verification tool, it will be to
Verifying source operand inputs model and reference model to be measured as input respectively, according to the output result of model to be measured and refers to mould
The output result of type is verified.
By enabling formal verification tool, model to be measured and reference are inputted respectively using source operand to be verified as input
Model before being verified according to the output result of the output result of model to be measured and reference model, judges source operation to be verified
Number whether belong to model to be measured it is all input in source operand have to verifying data, and source operand to be verified not
When belonging to necessary verifying source operand, directly determining and (do not enable formal verification tool, directly obtain verification result) will be to be verified
When source operand inputs model to be measured, the output result of model to be measured and the output that source operand to be verified is inputted to reference model
As a result equal, (partial state space is direct for the calculation amount for reducing during all state spaces for traversing model to be measured
To verification result), it is thus possible to while guaranteeing to verify completeness, the Formal Verification for reducing the embodiment of the present invention occurs
The risk of Space Explosion problem solves the problems, such as that the larger problem of risk of Space Explosion occurs in existing Formal Verification.
With reference to first aspect, in first aspect first embodiment, model to be measured is to execute addition or subtraction
Model, it is each that input source operand include the first source operand and the second source operand；Necessity verifies source operand
Refer to that the first source operand and the second source operand are normalized number.
With reference to first aspect, in first aspect second embodiment, model to be measured is to execute addition or subtraction
Model, it is each that input source operand include the first floating-point source operand and the second floating-point source operand；Necessary verifying source
Operand refers to that the exponent bits of the second floating-point source operand are more than or equal to the 1/2 of the exponent bits of the first floating-point source operand.
With reference to first aspect or first aspect first embodiment or first aspect second embodiment, in first aspect
In three embodiments, start formal verification tool, inputs model to be measured and reference respectively for source operand to be verified as input
Model, the step of verifying according to the output result of the output result of model to be measured and reference model, comprising: starting form is tested
Card tool, when verifying each can input source operand and input model and reference model to be measured respectively, the output result of model to be measured
It is whether all identical as the output result of reference model；If output result all phases of the output result of model to be measured and reference model
Together, then the verification result of model to be measured Yu reference model equivalence is exported.
Third embodiment with reference to first aspect, in the 4th embodiment of first aspect, Formal Verification further includes
Following steps: if the output result of model to be measured and the output result of reference model there are different, judge formal verification work
Tool whether there is mistake；If there are mistakes for formal verification tool, all source operands that input are carried out again after misarrangement
Verifying；If mistake is not present in formal verification tool, the verification result of model to be measured Yu reference model non-equivalence is exported.
According to second aspect, the embodiment of the invention provides a kind of formal verification devices, comprising: data acquisition module is used
In the source operand to be verified for obtaining input model to be measured；Data judgment module, for judging whether source operand to be verified belongs to
Source operand is verified in necessity, necessity verifying source operand is that can input all of model to be measured to input in source operand, must
The data that need be verified；As a result determining module, when source operand to be verified being inputted model to be measured for determining, model to be measured
It is equal with by the source operand to be verified input output result of reference model to export result；Reference model is positive shows mould to be measured really
The model of the function of type；Result verification module is distinguished for starting formal verification tool using source operand to be verified as input
Model and reference model to be measured are inputted, is verified according to the output result of the output result of model to be measured and reference model.
In conjunction with second aspect, in second aspect first embodiment, model to be measured is to execute addition or subtraction
Model, each to input source operand and include the first source operand and the second source operand, necessity verifying source operand is
Refer to that the first source operand and the second source operand are normalized number.
In conjunction with second aspect, in second aspect second embodiment, model to be measured is to execute addition or subtraction
Model, it is each that input source operand include the first floating-point source operand and the second floating-point source operand；Necessary verifying source
Operand refer to the exponent bits of the first floating-point source operand less than the second floating-point source operand exponent bits 1/2.
According to the third aspect, the embodiment of the invention provides a kind of formal verification platforms, comprising: memory and processor,
Connection is communicated with each other between the memory and the processor, and computer instruction, the processing are stored in the memory
Device is by executing the computer instruction, thereby executing described in any one of first aspect or first aspect embodiment
Formal Verification.
It is described computer-readable the embodiment of the invention provides a kind of computer readable storage medium according to fourth aspect
Storage medium stores computer instruction, and the computer instruction is for making the computer execute first aspect or first aspect
Any one embodiment described in Formal Verification.
Detailed description of the invention
It, below will be to specific in order to illustrate more clearly of the specific embodiment of the invention or technical solution in the prior art
Embodiment or attached drawing needed to be used in the description of the prior art be briefly described, it should be apparent that, it is described below
Attached drawing is some embodiments of the present invention, for those of ordinary skill in the art, before not making the creative labor
It puts, is also possible to obtain other drawings based on these drawings.
Fig. 1 is a kind of method flow diagram of Formal Verification provided in an embodiment of the present invention；
Fig. 2 is a kind of specific method flow chart of step S104 in Fig. 1；
Fig. 3 is another method flow diagram of formal verification analysis method provided in an embodiment of the present invention；
Fig. 4 a is a kind of scene schematic diagram of floating point arithmetic；
Fig. 4 b is another scene schematic diagram of floating point arithmetic；
Fig. 5 is a kind of functional block diagram of formal verification device provided in an embodiment of the present invention；
Fig. 6 is the hardware structural diagram of a kind of electronic equipment provided in an embodiment of the present invention.
Specific embodiment
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with the embodiment of the present invention
In attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is
A part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, those skilled in the art are not having
Every other embodiment obtained under the premise of creative work is made, shall fall within the protection scope of the present invention.
In the description of the present invention, it should be noted that term " first ", " second ", " third " are used for description purposes only,
It is not understood to indicate or imply relative importance.
Embodiment 1
Formal Verification provided in an embodiment of the present invention is applied to formal verification platform used in circuit design verification
In, which can enable reference model and environment to be measured with the verification environment of analog references model and model to be measured
It is enough to operate normally, and the corresponding instruction of the Formal Verification in the embodiment of the present invention is executed, verify whether model to be measured is realized
Its expected function.Specifically, the model to be measured in the embodiment of the present invention refers to register transfer level circuit (Register
Transfer Level, RTL) model, i.e., with the pumping of the circuit operation of hardware description language (Verilog or VHDL) description design
As model, reference model, which then refers to, writes capable of and ensuring just for foundation using high-level language (such as scripting language or C language)
Really the model of the expectation function of the circuit now designed.
Fig. 1 shows the flow chart of the Formal Verification of the embodiment of the present invention, as shown in Figure 1, this method may include
Following steps:
S101: the source operand to be verified for inputting model to be measured is obtained.Herein, source operand to be verified is model to be measured
All any datas inputted in source operand.
S102: judge whether source operand to be verified belongs to necessary verifying source operand.Herein, necessary verifying source operation
Number inputs in source operand for that can input all of model to be measured, it is necessary to which the data of verifying specifically pass through summary and induction
When all possibility input source operands are as input, the characteristic of the expected function of realizing of model to be measured and the output of model to be measured
As a result, sorting out to all possible input source operands, necessary verifying source operand is obtained.Herein, if source to be verified
Operand is not belonging to necessary verifying source operand, thens follow the steps S103；If source operand to be verified belongs to necessary verifying source
Operand thens follow the steps S104.
Specifically, be to realize addition (or subtraction) operation with the expected function of realizing of model to be measured, it is each can input source
For operand includes the first source operand and the second source operand, when the first source operand and the second source operand of input
When being normalized number, need to carry out specific operation, and when the first source operand of input or the second source operand are non-rule
Format several or special number (such as positive and negative infinite, non-number) when, the output result of model to be measured is error information；Meanwhile by
Be positive the model of the function of really existing model to be measured in reference model, therefore, the case where reference model with above-mentioned model to be measured
Situation is identical；Therefore, when the first source operand or the second source operand that can be inputted in source operand are in addition to normalized number
Unnomalized number in addition or it is special several when, can directly determine can input source operand as model to be measured when input for this
Output result it is equal with the output result of reference model, it can by the first source operand and the second source operand be specification
The source operand classification that inputs for changing number is divided into necessary verifying source operand.
Still by taking the expected function of realizing of model to be measured is to realize addition (or subtraction) operation as an example, when can input source operation
When the first source operand and the second source operand that number includes are normalized number, can also to necessity verifying source operand carry out into
The classification of one step.
Specifically, since computer is when carrying out operation to normalized number, it is generally converted into floating number, and for guarantor
The considerations of demonstrate,proving operation result precision, the precision of calculated result is generally consistent with the precision of source operand, therefore, when the first floating-point source
Operand is much larger than the second floating-point source operand, and result value range is greater than instruction permissible accuracy after two source operand superpositions
When value range, the least significant bit (LSB) of calculated result needs all to be rounded (rounding) operation, calculating at this time
As a result precision is substantially identical as the first floating-point source operand, especially when the exponent bits of the second floating-point source operand are less than first
The exponent bits of floating-point source operand 1/2 when, the second floating-point source operand does not influence calculated result substantially, can directly by
First floating-point source operand as calculated result, without by the first floating-point source operand and the input of the second floating-point source operand to
Model is surveyed to be calculated；The model of the function of really existing model to be measured, therefore, reference model simultaneously as reference model is positive
The case where with above-mentioned model to be measured the case where it is identical；Therefore, when the finger for the second floating-point source operand that can be inputted in source operand
Numerical digit less than the first floating-point source operand exponent bits 1/2 when, can directly determine by this can input source operand count it is defeated
The output result of fashionable model to be measured and the output result of reference model are equal, it can by the exponent bits of the second source operand
More than or equal to the first floating-point source operand exponent bits 1/2 when input source operand classification be divided into necessary verifying
Source operand.
S103: determine by source operand to be verified input model to be measured when, the output result of model to be measured with will be to be verified
The output result that source operand inputs reference model is equal.Herein, reference model is positive the function of really existing model to be measured
Model.
Herein, it uses the example above, necessity verifying source operand is normalized number, then when first in source operand to be verified
When source operand or the second source operand are unnomalized number or are special several, determine source operand to be verified input is to be measured
When model, the output result of model to be measured is equal with by the source operand to be verified input output result of reference model；If desired
When verifying source operand is that the exponent bits of the second source operand are more than or equal to the 1/2 of the exponent bits of the first floating-point source operand
Input source operand, then when the exponent bits of the second floating-point source operand less than the first floating-point source operand exponent bits 1/
When 2, determine by source operand to be verified input model to be measured when, the output result of model to be measured with source operand to be verified is defeated
The output result for entering reference model is equal.
It should be noted that source operand to be verified is not belonging to necessary verifying source operand, the source to be verified is not implied that
Operand does not need to be verified, and refer to the source operand to be verified according to do not need to be entered model and reference model to be measured into
Row be calculated output result after verify, so that it may directly obtain verifying conclusion (being different from necessary verifying source operand), i.e., this
The content that step executes still is a part of formal verification.
S104: source operand to be verified is inputted model to be measured and reference respectively by starting formal verification tool
Model is verified according to the output result of the output result of model to be measured and reference model.
Herein, formal verification tool is for providing the running environment of model and reference model to be measured, so that source to be verified
Operand as input input model and reference model to be measured respectively when, model and reference model to be measured can operate normally to
Calculated result is exported, meanwhile, formal verification tool is also used to verify the output result of model to be measured and the data knot of reference model
Whether fruit is equal.Concrete configuration mode, function and the function sentence of formal verification tool belong to the prior art, herein no longer
It repeats.
Herein, when the output result of model to be measured is equal with the output result of reference model, export model to be measured with
The verification result of reference model equivalence；It is when the output result of the output result of model to be measured and reference model is unequal, then defeated
The verification result of formal verification tool error or model to be measured and reference model non-equivalence out.In concrete application scene, when
When the output result of model to be measured and the unequal output result of reference model, can also further to formal verification tool into
Row misarrangement, finally obtains the verification result of formal verification tool error, or obtains reference model and reference model non-equivalence
Verification result.
The Formal Verification of the embodiment of the present invention, by enabling formal verification tool verifying source operand work to be verified
When inputting model and reference model to be measured respectively for input, whether the output result of the output result of model to be measured and reference model
Before equal, judge source operand to be verified whether belong to model to be measured it is all input in source operand have to verifying
Data, and when source operand to be verified is not belonging to necessary verifying source operand, directly determine (formal verification tool is not enabled,
Directly obtain verification result) by source operand to be verified input model to be measured when, the output result of model to be measured with will be to be verified
The output result that source operand inputs reference model is equal, during reducing all state spaces for traversing model to be measured
Calculation amount (partial state space directly obtains verification result), it is thus possible to while guaranteeing to verify completeness, reduce this hair
There is the risk of Space Explosion problem in the Formal Verification of bright embodiment, and solving existing Formal Verification, space occur quick-fried
The larger problem of the risk of fried problem.
As a kind of optional embodiment of the embodiment of the present invention, as shown in Fig. 2, step S104 may include walking as follows
It is rapid:
S201: starting formal verification tool, verifying can each input source operand and input model to be measured respectively and with reference to mould
When type, whether the output result of model to be measured and the output result of reference model are all identical.Herein, if model to be measured it is defeated
Result and the output result of reference model are all identical out, then follow the steps S202；If the output result of model to be measured and reference
There is difference in the output result of model, then follow the steps S203.
S202: the verification result of model to be measured Yu reference model equivalence is exported.
S203: judge formal verification tool with the presence or absence of mistake.Herein, if formal verification tool is there are mistake,
Execute step S204；If mistake is not present in formal verification tool, S205 is thened follow the steps.
S204: it inputs source operand to all after misarrangement and is verified again.Herein, it is re-execute the steps after misarrangement
S101- step S104 (S201-S205 that step S104 includes), until exporting model and reference model equivalence to be measured or differing
The formal verification result of valence.
S205: the verification result of model to be measured Yu reference model non-equivalence is exported.
Fig. 3 shows the flow chart of Formal Verification according to another embodiment of the present invention, is to execute with model to be measured
The model of addition or subtraction, it is each to input source operand and include the first floating-point source operand and the second floating-point source behaviour
The Formal Verification of the embodiment of the present invention is described for counting, as shown in figure 3, this method may include steps of:
S301: the source operand to be verified for inputting model to be measured is obtained.Herein, source operand to be verified is model to be measured
All any datas inputted in source operand.
S302: it is floating to judge whether the index of the second floating-point source operand in source operand to be verified is greater than or equal to first
The 1/2 of the index of point source operand.Herein, if the index of the second floating-point source operand is less than the first floating-point source operand
The 1/2 of index, thens follow the steps S303；If the index of the second floating-point source operand is operated more than or equal to the first floating-point source
The 1/2 of several indexes, thens follow the steps S304.
S303: determine by source operand to be verified input model to be measured when, the output result of model to be measured with will be to be verified
The output result that source operand inputs reference model is equal.Herein, reference model is positive the function of really existing model to be measured
Model.
Herein, since computer is when carrying out operation to normalized number, it is generally converted into floating number, and for guarantor
The considerations of demonstrate,proving operation result precision, the precision of calculated result is generally consistent with the precision of source operand, thus, as shown in fig. 4 a,
When a floating number src1 is much larger than second floating number src2, that is to say, that have gap between two source operands
(gap) when, the value range of two superimposed results of floating number (result) is greater than instruction permissible accuracy value range, that
The least significant bit (LSB) of result (result) needs all to be rounded (rounding) operation at this time, at this time result
Precision is equal with src1 substantially, and especially when the exponent bits of src2 are less than the 1/2 of src1 exponent bits, src2 is to calculated result base
This is not influenced, and calculated result is directly denoted as src1, therefore, when the second floating-point source operand in source operand to be verified
Index less than the first floating-point source operand index 1/2, and using source operand to be verified as input input respectively it is to be measured
When model and reference model, the output result of model to be measured and the output result of reference model are the first floating-point source operand,
Therefore, can directly determine by source operand to be verified input model to be measured when, the output result of model to be measured with will be to be verified
The output result that source operand inputs reference model is equal.
S304: starting formal verification tool, verifying can each input source operand and input model to be measured respectively and with reference to mould
When type, whether the output result of model to be measured and the output result of reference model are all identical.Herein, if model to be measured it is defeated
Result and the output result of reference model are all identical out, then follow the steps S305；If the output result of model to be measured and reference
There is difference in the output result of model, then follow the steps S306.
Herein, range is less than or equal to as a result, as shown in Figure 4 b after two floating number value ranges are superimposed
When the value range of src1 can have Chong Die (overlap) with src2, need to calculate and verify according to normal calculation methods, because
This needs to start when the index of the second floating-point source operand is more than or equal to the 1/2 of the index of the first floating-point source operand
Formal verification tool, when verifying source operand to be verified and inputting model and reference model to be measured respectively as input, model to be measured
Output result and reference model output result it is whether all identical.
S305: the verification result of model to be measured Yu reference model equivalence is exported.
S306: judge formal verification tool with the presence or absence of mistake.Herein, if formal verification tool is there are mistake,
Execute step S307；If mistake is not present in formal verification tool, S308 is thened follow the steps.
S307: it inputs source operand to all after misarrangement and is verified again.Herein, it is re-execute the steps after misarrangement
S301- step S307, until the formal verification result of output equivalence or non-equivalence.
S308: the verification result of model to be measured Yu reference model non-equivalence is exported.
In embodiments of the present invention, by being the addition or subtraction for executing Basis of Computer Engineering in model to be measured, and
Model to be measured inputs (including the first floating-point source operand and the second floating-point source under the premise of source operand belongs to normalized number
Operand), further judged that can input source operand and whether belong to necessary verifying source operand, can further be subtracted
The calculation amount during all state spaces of model to be measured is traversed less, while guaranteeing to verify completeness, reduces this hair
There is the risk of Space Explosion problem in the Formal Verification of bright embodiment.
Embodiment 2
Fig. 5 shows a kind of functional block diagram of formal verification device of the embodiment of the present invention, which can be used to implement
Formal Verification described in embodiment 1 or its any optional embodiment.As shown in figure 5, the device includes: data acquisition
Module 10, data judgment module 20, as a result determining module 30 and result verification module 40.
Data acquisition module 10 is for obtaining the source operand to be verified for inputting model to be measured.
Data judgment module 20 is for judging whether source operand to be verified belongs to necessary verifying source operand, necessity verifying
Source operand is that can input all of model to be measured to input in source operand, it is necessary to the data of verifying.Herein, if to
Verifying source operand is not belonging to necessary verifying source operand, then implementing result determining module 30；If source operand category to be verified
Source operand is verified in necessity, then implementing result authentication module 40.
As a result when source operand to be verified is inputted model to be measured for determining by determining module 30, the output knot of model to be measured
Fruit is equal with by the source operand to be verified input output result of reference model.Herein, reference model is positive really existing to be measured
The model of the function of model.
Result verification module 40 for starting formal verification tool, using source operand to be verified as input input respectively to
Model and reference model are surveyed, is verified according to the output result of the output result of model to be measured and reference model.
The formal verification device of the embodiment of the present invention, by enabling formal verification tool verifying source operand work to be verified
When inputting model and reference model to be measured respectively for input, whether the output result of the output result of model to be measured and reference model
Before equal, judge source operand to be verified whether belong to model to be measured it is all input in source operand have to verifying
Data, and when source operand to be verified is not belonging to necessary verifying source operand, directly determine (formal verification tool is not enabled,
Directly obtain verification result) by source operand to be verified input model to be measured when, the output result of model to be measured with will be to be verified
The output result that source operand inputs reference model is equal, during reducing all state spaces for traversing model to be measured
Calculation amount (partial state space directly obtains verification result), it is thus possible to while guaranteeing to verify completeness, reduce this hair
There is the risk of Space Explosion problem in the Formal Verification of bright embodiment, and solving existing Formal Verification, space occur quick-fried
The larger problem of the risk of fried problem.
As a kind of optional embodiment of the embodiment of the present invention, model to be measured is the mould for executing addition or subtraction
Type, each to input source operand and include the first source operand and the second source operand, necessity verifying source operand refers to the
One source operand and the second source operand are normalized number.
As a kind of optional embodiment of the embodiment of the present invention, model to be measured is the mould for executing addition or subtraction
Type, each to input source operand include the first floating-point source operand and the second floating-point source operand；Necessary verifying source operation
Number refer to the exponent bits of the first floating-point source operand less than the second floating-point source operand exponent bits 1/2.
The embodiment of the invention also provides a kind of electronic equipment, as shown in fig. 6, the electronic equipment may include processor 61
With memory 62, wherein processor 61 can be connected with memory 62 by bus or other modes, to pass through bus in Fig. 6
For connection.
Processor 61 can be central processing unit (Central Processing Unit, CPU).Processor 61 can be with
For other general processors, digital signal processor (Digital Signal Processor, DSP), specific integrated circuit
(Application Specific Integrated Circuit, ASIC), field programmable gate array (Field-
Programmable Gate Array, FPGA) either other programmable logic device, discrete gate or transistor logic,
The combination of the chips such as discrete hardware components or above-mentioned all kinds of chips.
Memory 62 is used as a kind of non-transient computer readable storage medium, can be used for storing non-transient software program, non-
Transient computer executable program and module, such as the corresponding program instruction/mould of the Formal Verification in the embodiment of the present invention
Block (data acquisition module 10 in such as Fig. 5, data judgment module 20, as a result determining module 30 and result verification module 40).Place
Non-transient software program, instruction and the module that reason device 61 is stored in memory 62 by operation, thereby executing processor
Various function application and data processing, i.e. Formal Verification in realization above method embodiment.
Memory 62 may include storing program area and storage data area, wherein storing program area can storage program area,
Application program required at least one function；It storage data area can the data etc. that are created of storage processor 61.In addition, storage
Device 62 may include high-speed random access memory, can also include non-transient memory, for example, at least a magnetic disk storage
Part, flush memory device or other non-transient solid-state memories.In some embodiments, it includes relative to place that memory 62 is optional
The remotely located memory of device 61 is managed, these remote memories can pass through network connection to processor 61.The reality of above-mentioned network
Example includes but is not limited to internet, intranet, local area network, mobile radio communication and combinations thereof.
One or more of modules are stored in the memory 62, when being executed by the processor 61, are executed
Formal Verification in b illustrated embodiment picture 1-4.
Above-mentioned electronic equipment detail can correspond to the corresponding associated description into embodiment shown in Fig. 4 b refering to fig. 1
Understood with effect, details are not described herein again.
It is that can lead to it will be understood by those skilled in the art that realizing all or part of the process in above-described embodiment method
Computer program is crossed to instruct relevant hardware and complete, the program can be stored in a computer-readable storage medium
In, the program is when being executed, it may include such as the process of the embodiment of above-mentioned each method.Wherein, the storage medium can for magnetic disk,
CD, read-only memory (Read-Only Memory, ROM), random access memory (Random Access
Memory, RAM), flash memory (Flash Memory), hard disk (Hard Disk Drive, abbreviation: HDD) or solid state hard disk
(Solid-State Drive, SSD) etc.；The storage medium can also include the combination of the memory of mentioned kind.
Obviously, the above embodiments are merely examples for clarifying the description, and does not limit the embodiments.It is right
For those of ordinary skill in the art, can also make on the basis of the above description it is other it is various forms of variation or
It changes.There is no necessity and possibility to exhaust all the enbodiments.And it is extended from this it is obvious variation or
It changes still within the protection scope of the invention.
Claims (10)
1. a kind of Formal Verification, which comprises the steps of:
Obtain the source operand to be verified for inputting model to be measured；
Judge whether the source operand to be verified belongs to necessary verifying source operand, the necessary verifying source operand is can be defeated
Enter described all of model to be measured to input in source operand, it is necessary to the data of verifying；
If the source operand to be verified is not belonging to the necessary verifying source operand, it is determined that operate the source to be verified
When number inputs the model to be measured, the output result of the model to be measured inputs the defeated of reference model with by source operand to be verified
Result is equal out；The reference model is positive shows the model of the function of the model to be measured really；
If the source operand to be verified belongs to the necessary verifying source operand, start formal verification tool, it will be described
Source operand to be verified inputs model and reference model to be measured as input respectively, according to the output result of the model to be measured with
The output result of the reference model is verified.
2. Formal Verification according to claim 1, which is characterized in that the model to be measured is to execute addition or subtract
The model of method operation, each described can to input source operand include the first source operand and the second source operand；Described necessity
Verifying source operand refers to first source operand and the second source operand is normalized number.
3. Formal Verification according to claim 1, which is characterized in that the model to be measured is to execute addition or subtract
The model of method operation, each described can to input source operand include the first floating-point source operand and the second floating-point source operand；
The necessary verifying source operand refers to that the exponent bits of the second floating-point source operand are more than or equal to first floating-point
The 1/2 of the exponent bits of source operand.
4. Formal Verification according to claim 1-3, which is characterized in that the starting formal verification work
Tool inputs model and reference model to be measured for the source operand to be verified as input, according to the model to be measured respectively
The step of output result and the output result of the reference model are verified, comprising:
Start formal verification tool, when judgement can each input source operand and input the model to be measured and reference model respectively,
Whether the output result of the model to be measured and the output result of the reference model are all identical；
If the output result of the model to be measured and the output result of the reference model are all identical, the mould to be measured is exported
The verification result of type and the reference model equivalence.
5. Formal Verification according to claim 4, which is characterized in that further include following steps:
If the output result of the model to be measured and the output result of the reference model there are different, judge the form
Verification tool whether there is mistake；
If there are mistakes for the formal verification tool, described input source operand to all after misarrangement and tested again
Card；
If mistake is not present in the formal verification tool, testing for the model to be measured and the reference model non-equivalence is exported
Demonstrate,prove result.
6. a kind of formal verification device characterized by comprising
Data acquisition module, for obtaining the source operand to be verified for inputting model to be measured；
Data judgment module, for judging whether the source operand to be verified belongs to necessary verifying source operand, described necessity
Verifying source operand is that can input described all of model to be measured to input in source operand, it is necessary to the data of verifying；
As a result determining module, when the source operand to be verified being inputted the model to be measured for determining, the model to be measured
Output result with by source operand to be verified input the output result of reference model it is equal；The reference model is positive really existing
The model of the function of the model to be measured；
Result verification module, for starting formal verification tool, using the source operand to be verified as input input respectively to
Model and reference model are surveyed, is verified according to the output result of the model to be measured and the output result of the reference model.
7. formal verification device according to claim 6, which is characterized in that the model to be measured is to execute addition or subtract
The model of method operation, each described can to input source operand include the first source operand and the second source operand, described necessity
Verifying source operand refers to first source operand and the second source operand is normalized number.
8. formal verification device according to claim 6, which is characterized in that the model to be measured is to execute addition or subtract
The model of method operation, each described can to input source operand include the first floating-point source operand and the second floating-point source operand；
The necessary verifying source operand refers to that the exponent bits of the second floating-point source operand are more than or equal to first floating-point
The 1/2 of the exponent bits of source operand.
9. a kind of formal verification platform characterized by comprising memory and processor, the memory and the processor
Between communicate with each other connection, be stored with computer instruction in the memory, the processor refers to by executing the computer
It enables, thereby executing the described in any item Formal Verifications of claim 1-5.
10. a kind of computer readable storage medium, which is characterized in that the computer-readable recording medium storage has computer to refer to
It enables, the computer instruction is for making the computer perform claim require the described in any item Formal Verifications of 1-5.
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| CN110311977A (en) * | 2019-07-01 | 2019-10-08 | 成都奥卡思微电科技有限公司 | A kind of formal verification platform and its method based on cloud computing |
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