CN104615808B - A kind of test method and reference model device of hardware computation component to be tested - Google Patents
A kind of test method and reference model device of hardware computation component to be tested Download PDFInfo
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Abstract
The invention discloses a kind of test methods and reference model device of hardware computation component to be tested.The reference model device includes：Instruction decoding module is used to instruct into row decoding input；Special data processing module is handled special data operation according to decoding result；Normal data processing module, according to decoding as a result, by the way that computing module is called to handle normal data operation；Operation result by the way that hardware platform resource is called to perform correspondingly operation, and is returned to normal data processing module by computing module；Flowing water control module is used to implement pipelining-stage control；Output module, for the result for exporting special data processing module, normal data processing module obtains.The characteristics of present invention further investigation arithmetic unit, the advantages of dexterously System Verilog and C language are combined, make full use of both language, the reference model needed for foundation rapidly and efficiently.
Description
Technical field
The invention belongs to the verification technique fields in integrated circuit, exactly, are related to setting for arithmetic unit reference model
Meter.
Background technology
With being constantly progressive for chip manufacturing process, chip feature sizes have been enter into the sub-micro epoch.At present, foundry
The representative value of most advanced technique that factory can provide is in 28nm or so.The scale of digital integrated electronic circuit is increasing, and integrated level is more next
Higher, inner space state is more and more and becomes increasingly complex, and the result that such present situation is brought is exactly chip functions and logic
The probability of error greatly increases.To ensure the correctness of chip design and the reusability of IP, verification just plays critical
Effect.From International Business Machines Corporation, technical data disclosed in the international advanced chip companies such as Intel and Advanced Micro Devices Inc.
It sees, at present in a chip design, the heavy workload of verification accounts for about the 60%~70% of amount of work, certain based on IP reuse
ASIC design in, this numerical value is even as high as more than 80%.In general, the means of verification include formal verification and analog simulation is tested
Card.Formal verification utilizes mathematical theorem and representation method, and design is derived and final certification design meets design specification.Simulation
The means of generally use, easily pinpoint the problems at the beginning of design at the beginning of simulating, verifying is design, and are verified suitable for black box.
In analog simulation verification method, emphasis is the behavior for how efficiently finding not meeting design specification, and artificial debugging is only applicable to
Very small data volume, inefficient, designer may use when initially completing hardware computation part codes to be tested；From
The verification platform of dynamicization is the guarantee of big data quantity verification.
Arithmetic unit mainly does data logic and arithmetical operation, and common arithmetic unit has：Pinpoint adder-subtractor, fixed point
Multiplier, fixed-point divider, floating-point adder-subtractor, floating-point multiplier etc.；Some projects may also need to more efficient operation
Component, if fixed point multiplies accumulating, floating-point multiply-accumulator etc..System Verilog have the ability of advanced modeling, and syntax rule is
The superset of Verilog.Compared to SystemC, System Verilog are easier to describe the relevant logic of certain hardware bottom layers, such as
The logic of step-by-step；And it is very convenient to communicate with RTL, can directly in a System Verilog/Verilog module,
Directly by System Verilog reference models and Verilog hardware computation device instantiations to be tested, this point is put down to testing
Building for platform is very good.
In ieee standard, System Verilog can in several ways, as DPI, PLI etc. communicate with C/C++.
System Verilog are because have the ability of bottom hardware description, and can facilitate and data are done with some high level conversions (such as
Realtobits), the control logic of reference model can be realized, special data is handled, the functions such as pipelining-stage control, and C/C++
It can realize the operation of normal data in reference model, it is only necessary to write corresponding function or call existing software.
Verification platform is as shown in Figure 1, basic principle is under input stimulus, to hardware computation component to be tested and with reference to mould
The output of type is compared and does interpretation of result, and whole flow process can be full-automatic or have a small amount of artificial participation.101 are
The input of test vector can be that constraint is random or hand-written, and constraint can generate excitation fast automaticly at random, it is hand-written can
To be random supplement, situation about not being tested specifically for some.102 be reference model, is that designer advises according to design
The System-Level Model that model demand is write, it is consistent with 103 hardware computation unit interfaces to be tested and function.104 are referred to by comparing
The output of model and the output of hardware computation component to be tested, when the two output is inconsistent, with the side such as figure or text
Formula reports all tune such as the data and command code that mistake occurs, hardware computation member interior space state to be tested to designer
Try the information needed.
Invention content
(1) technical problems to be solved
In view of this, it is a primary object of the present invention to provide a kind of design side of efficient arithmetic unit reference model
Method shortens proving period.
(2) technical solution
For this purpose, the present invention provides a kind of reference model device of hardware computation unit test to be tested, including：
Instruction decoding module is used to instruct into row decoding input；
Special data processing module is handled special data operation according to decoding result；
Normal data processing module, according to decoding as a result, by call computing module to normal data operation at
Reason；
Computing module by the way that hardware platform resource is called to perform correspondingly operation, and operation result is returned to normally
Data processing module；
Flowing water control module is used to implement pipelining-stage control；
Output module, for the result for exporting special data processing module, normal data processing module obtains.
The present invention also provides a kind of test method of hardware computation component to be tested, including：
Step 1 receives test vector, and the test vector includes carrying out the instruction of predetermined operation and corresponding operating number；
Step 2, using System Verilog to the test vector into row decoding；
Step 3 determines that special data processing or normal data are handled according to decoding result；
Step 4, if special data handle, then it is handled using System Verilog；It is if normal
Data processing then handles it using C function, and obtains test result；
Test result and the operation result of the hardware computation component to be tested are compared by step 5, obtain test knot
Fruit.
(3) advantageous effect
It can be seen from the above technical proposal that the invention has the advantages that：
The characteristics of maximum feature of the present invention is further investigation arithmetic unit, on existing hardware and software platform, efficiently
Establish the reference model that design to be measured is wanted.In the concrete realization, successfully different designs institute is established using this method
The arithmetic unit reference model needed, Reference Model Design have combined third party's commercialization hardware and software platform and have realized according to actual needs.
Before, in a certain case, the Reference Model Design of an arithmetic unit needs several weeks or longer time, using the present invention
Method realizes that the time can foreshorten to half a day to one day, greatly improve the efficiency, and save the unnecessary duplication of labour.
As shown in figure 3, single double precision multiplexing floating-point multiplication reference model size of code that method using the present invention is established is only
It is 10% or so of hardware computation part design to be tested, the verification amount compared to hardware computation component to be tested greatly reduces, and
And reference model only needs to realize Instruction decoding, special data processing, control and flowing water, arithmetic section can be combined using C language
Existing multi-party hardware and software platform, the correctness and reliability of reference model can ensure very well, it be verified relatively easy.Ginseng
The processing of general data in model is examined due to calling C function, C function is realized by external software and hardware, it is only necessary to which every instruction is done
A small amount of general data and special data test, you can ensure the correctness of reference model.
Description of the drawings
The flow diagram that analog simulation is verified when Fig. 1 is test chip；
Fig. 2 is the circuit theory schematic diagram of reference model device in the present invention；
Fig. 3 is reference model device size of code and hardware computation part codes amount comparison schematic diagram to be tested in the present invention.
Specific embodiment
To make the objectives, technical solutions, and advantages of the present invention clearer, below in conjunction with specific embodiment, and reference
Attached drawing, the present invention is described in further detail.
In the floating-point multiplier of the single double precision multiplexing of design, provide, use according to 754 standard rounding procedures of IEEE
System Verilog language directly writes floating-point multiplication, and rounding mode control can not be carried out directly in high level description,
Assume A, B, C is three double-precision floating points, when C=A*B sentences are write in System Verilog, is unable to control rounding-off
Mode.If with more bottom, such as the mode of step-by-step description, then the complexity of reference model greatly increases, and verifies that it is correct
Property workload no less than the workload for verifying hardware computation part design correctness to be tested.
As shown in Fig. 2, the present invention is combined by System Verilog and C language, existing software and hardware item is made full use of
Part realizes arithmetic unit Reference Model Design.The present invention provides a kind of references for hardware computation unit test to be tested
Model equipment, including：
Instruction decoding module 201 is used to instruct into row decoding input；Specifically, described instruction decoding module 201 is right
Input is instructed into row decoding, obtains action type, and action type is operated including fixed and floating, operation bit wide, integer/decimal type,
Whether there is the contents such as symbol, rounding procedure.Wherein, fixed and floating operation can be fixed and floating ALU operations, and fixed and floating multiplying is fixed
The types such as floating multiplication accumulating operation；Operation bit wide can be fixed point 8,16, either single double precision or the expansion of the bit wides such as 32
Open up accuracy floating-point bit wide；Integer/decimal type is indicated as being integer operation or decimal operation；Whether there is symbol and be indicated as being signed number
Or unsigned number operation；Rounding procedure indicates fixed point results as saturated process or truncation, floating point result rounding treatment
Mode for rounding-off nearby, to modes such as zero rounding-off, just infinite rounding-off or negative infinite rounding-offs.
Special data processing module 202, is used to carrying out special data processing, for example the operand in floating-point operation includes
It is by part progress operation when inputs for infinite, non-number, 0, for the operation result of special data, according to its use environment
Defined instruction specification carries out.
Normal data processing module 203 by calling respective function, handles normal data, passes through communication interface 207
Data interaction and communication are carried out with computing module 204, the modes such as DPI, PLI or other communications may be used in communication interface 207
Mode is realized；
Computing module 204 its by the way that hardware platform resource is called to perform correspondingly operation, and operation result is returned to just
Regular data processing module；It calls existing hardware platform resource by C function, and the communication interface 207 passes to C function institute
The instructions such as the parameter needed, two operands and rounding procedure as needed for floating-point multiplication, the C function of computing module 204
Respective handling is carried out to input data according to instruction, result of calculation, such as multiplication result is obtained, can pass through when implementing
The instruction that compilation directly invokes existing hardware platform realizes that existing hardware platform can be diversified forms, for example X 86 processor puts down
Platform, CUDA platforms or other disclosure satisfy that the various commercial hardware and software platforms such as the simulator platform of increasing income of demand, as a result accurately
Specification, it is small compared to hardware computation part design size of code to be tested, such as carried out under various rounding procedures on X 86 processor platform
Single double-precision floating point multiplying, C function complete operation by forms such as C inline assemblies, obtain correct operation result.Communication
Operation result is returned to normal data processing module 203 by interface 207.
Flowing water control module 205, is used to implement the logic controls such as pipelining-stage control, pipeline register, in reference model
Portion's pipelining-stage is consistent with hardware computation part design pipelining-stage to be tested, to ensure that cycle stage accurate reference model designs.
Output module 206, for special data processing module 202, normal data processing module 203 acquisition through flowing water
The result of control module 205 is selected and is exported after doing necessary processing according to design specification.
In above device, described instruction decoding module 201, special data processing module 202, normal data processing module
203rd, flowing water control module 205 and output module 206 are realized using System Verilog.System Verilog have
The ability of bottom hardware description, and can facilitate and data are done with some high level conversions (such as realtobits), it can realize ginseng
Examine the functions such as the control logic of model, special data processing, pipelining-stage control.
In addition, the computing module 204 is realized by C function, since C function can directly invoke the finger of existing hardware platform
It enables and realizes concrete operation, result of calculation 100% is accurate, realizes that size of code is small compared to System Verilog, function accuracy is easy
Ensure, speed is fast, and it is few to expend resource.Method using the present invention, the side being combined using System Verilog and C language
Formula carries out reference model realization.As shown in figure 3, the final size of code of the reference model is only hardware computation part design to be tested
8.8%, in System Verilog models realize Instruction decoding, Pipeline control and special data processing etc. particular designs
Defined function, this partial code are mainly some control logics, and correctness is easier to verify.And the calculating part of normal floating-point
Point, existing C function is called to realize by way of DPI, it only need to be into line function sound in System Verilog models
Bright and calling.C function can facilitate the control realized and be rounded to floating-point multiplication, for example, in X86 architecture platforms, C
When function is realized, the rounding-off flag bit of X86 floating-point operations is controlled to can obtain the operation result of different rounding procedures by setting,
This function only needs a few row X86 inline assembly codes can be realized.
It was verified that this method is simple, efficient, designer needs to spend 1 month or more time completion is to be measured
Examination hardware computation part design is write, and the foundation of reference model only needs 0.5 day time can be completed, and reference model has
Very high correctness and reliability provides a strong guarantee the verification of hardware computation part design correctness to be tested.
The present invention also provides a kind of test method of hardware computation component to be tested, including：
Step 1 receives test vector, and the test vector includes carrying out the instruction of predetermined operation and corresponding operating number；
Step 2, using System Verilog to the test vector into row decoding；
Step 3 determines that special data processing or normal data are handled according to decoding result；
Step 4, if special data handle, then it is handled using System Verilog；It is if normal
Data processing then calls C function to handle it, and obtains test result；
Test result and the operation result of the hardware computation component to be tested are compared by step 5, obtain test knot
Fruit.
Specific implementation details in the above method is consistent with the above-mentioned description to test model device, and details are not described herein.
Particular embodiments described above has carried out the purpose of the present invention, technical solution and advantageous effect further in detail
Describe in detail bright, it should be understood that the above is only a specific embodiment of the present invention, is not intended to restrict the invention, it is all
Within the spirit and principles in the present invention, any modification, equivalent substitution, improvement and etc. done should be included in the protection of the present invention
Within the scope of.
Claims (7)
1. a kind of reference model device of hardware computation unit test to be tested, including：
Instruction decoding module is used to instruct into row decoding input；
Special data processing module is handled special data operation according to decoding result；
Normal data processing module, according to decoding as a result, by the way that computing module is called to handle normal data operation；
Operation result by the way that hardware platform resource is called to perform correspondingly operation, and is returned to normal data by computing module
Processing module；
Flowing water control module is used to implement pipelining-stage control；
Output module, for the result for exporting special data processing module, normal data processing module obtains；
Wherein, described instruction decoding module, special data processing module, normal data processing module, flowing water control module and defeated
Go out module to realize using SystemVerilog；The computing module calls the execution of hardware platform resource correspondingly to transport by C function
It calculates.
2. reference model device as described in claim 1, wherein, the special data processing includes the operation in floating-point operation
Operation when number is infinite, non-number or 0.
3. reference model device as described in claim 1, further includes：
Communication interface, for the data interaction and communication between normal data processing module and computing module.
4. reference model device as claimed in claim 3, wherein, the communication interface is realized using DPI or PLI modes.
5. a kind of test method of hardware computation component to be tested, including：
Step 1 receives test vector, and the test vector includes carrying out the instruction of predetermined operation and corresponding operating number；
Step 2, using SystemVerilog to the test vector into row decoding；
Step 3 determines that special data processing or normal data are handled according to decoding result；
Step 4, if special data handle, then it is handled using SystemVerilog；If at normal data
Reason, then handled it using C function, and obtain test result；
Test result and the operation result of the hardware computation component to be tested are compared by step 5, obtain test result.
6. method as claimed in claim 5, wherein, in step 4, the special data processing includes the operation in floating-point operation
Operation when number is infinite, non-number or 0.
7. method as claimed in claim 5, wherein, if normal data is handled in step 4, then pass through tune using C function
Correspondingly operation is performed with hardware platform resource.
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| CN106708687B (en) * | 2015-11-12 | 2020-03-17 | 青岛海信电器股份有限公司 | Chip verification method and device based on executable file |
| CN109829192B (en) * | 2018-12-26 | 2023-10-17 | 合芯科技(苏州)有限公司 | Reference model construction method and device for processor computing unit |
| CN109933948B (en) * | 2019-04-01 | 2024-02-02 | 合芯科技(苏州)有限公司 | Form verification method, device, form verification platform and readable storage medium |
| CN112241347B (en) * | 2020-10-20 | 2021-08-27 | 海光信息技术股份有限公司 | Method for realizing SystemC verification and verification platform assembly architecture |
| CN112464498B (en) * | 2020-12-24 | 2021-11-09 | 芯天下技术股份有限公司 | True modeling verification method and device for memory, storage medium and terminal |
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