CN101008962A - Verification method for configurable and replaceable reference model used by network chip - Google Patents
Verification method for configurable and replaceable reference model used by network chip Download PDFInfo
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- CN101008962A CN101008962A CN 200610063601 CN200610063601A CN101008962A CN 101008962 A CN101008962 A CN 101008962A CN 200610063601 CN200610063601 CN 200610063601 CN 200610063601 A CN200610063601 A CN 200610063601A CN 101008962 A CN101008962 A CN 101008962A
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Abstract
This invention relates to one validation method to set place network chip user reference module, which comprises the following steps: through adding module interface files in reference module and using condition coding and extracting reference module in coding process; establishing imbed design module reference module to achieve easy place use reference module to improve validation efficiency and to reduce validation work volume.
Description
Technical field
The present invention relates to the reference model of network switch chip checking, mainly be meant a kind of verification method for configurable and replaceable reference model used by network chip.
Background technology
In recent years, internet develop rapidly.Along with rapid development of Internet, the use of the network switch is also more and more wider, and the scale of network exchanging chip is also increasing, up to ten million easily door, and tens modules, the checking of chip functions also become to become increasingly complex.
When chip design was verified, the application reference model was the method that is in daily use.Fig. 1 is the scheme block diagram of typical application reference model to design verification to be measured.
Various test vectors are circulated into excitation in design to be measured and the reference model by bus functional model, by bus functional model the response of design to be measured and the response of reference model are converted into observable form (such as text) again, to confirming after the interpretation of result that whether design to be measured is by checking.
Because the increase of chip-scale, increasing of chip internal module number makes usually to be difficult to orientation problem and solution in the mode that designs top layer application reference model.Such as in the exchange chip of the 24+2 that the present invention relates to, the mistake that occurs at port module, and its result of mistake who occurs in memory management module shows as and can't exchange will be located the errors present quite difficulty that becomes.
Secondly, because module number is more, the circuit scale of module is also bigger, and individual module is often finished by each independent project team, in whole design also imperfect tense, has to set up test platform separately, writes test vector separately.Cause the workload of project teams to strengthen, simultaneously can't assurance function in system-level correctness.Such as in the 24+2 exchange chip that the present invention relates to, the project team of design port module has to verify in the memory management module of design initial development of virtual whether the processing of its data is normal, and the have to port model of development of virtual of the project team of design memory management module provides its test and excitation.Such authentication policy is inefficiency but also can not guarantee correctness not only, and the test platform and the test vector of each module spended time exploitation just cancel when system debug fully, are not worth, and not can be described as serious waste.
Summary of the invention
The purpose of this invention is to provide a kind of verification method for configurable and replaceable reference model used by network chip, be embedded in the reference model by module design to be measured, test vector is circulated into reference model by bus functional model and includes in the reference model of design module to be measured, its response resolves to analyzable form (such as text) by bus functional model, the replacement of module and configuration are specified (such as-m module name) by the action command line parameter, compiler directive is set in code, receive the instruction of band module name, the reference model file destination of then setting up embedded this module participates in emulation, has solved the defective that prior art exists preferably.
Realize that technical scheme of the present invention is: this verification method comprises modeling method and configuration parameter, is characterized in that described method comprises module to be verified is embedded in the reference model, replaces and verify module undetermined by parameter.
This technical scheme also comprises:
Described method comprises that also test vector is circulated into reference model by bus functional model and includes in the reference model of design module to be measured, its response resolves to analyzable textual form by bus functional model, the replacement of module is specified by the action command line parameter with configuration, compiler directive is set in code, receive the instruction of band module name, the reference model file destination of then setting up embedded this module participates in emulation.
Described method also comprises the following steps
By keeping same hierarchical structure with design during reference model in exploitation, promptly possess same Module Division, realize that reference model is embedded and replace design document;
Establish the module that reference model need embed, and extract the interface signal of each module, set up interface document;
Set up the conditional compilation code in the reference model top layer, extract the compiling parameter, the interface document substitution with this module when compiling compiles.
The beneficial effect that the present invention has: the proof scheme after the improvement becomes very easy when each submodule problem of positioning chip, has reduced the scope of analyzing greatly.Such as in the 24+2 exchange chip that the present invention relates to, be embedded in the reference model that empirical tests has been passed through by code port module, if its response goes wrong, the designer can be absorbed in analysis port module and interface thereof, and unnecessaryly goes to suspect other modules.
Secondly, the proof scheme after the improvement to each submodule project team can application system test vector and test platform, and unnecessary exploitation voluntarily test vector and test platform separately.Such as in the 24+2 exchange chip that relates to, the project team of memory management module only need be embedded into module in the reference model, just can obtain the excitation that it is wanted by system-level test vector, the response analysis instrument of application system level can be verified this module very easily again.
Description of drawings
Fig. 1 is the scheme block diagram of traditional application reference model to design verification to be measured.
Fig. 2 is a proof scheme block diagram of the present invention.
Fig. 3 is the simple and clear block diagram of proof procedure of the present invention.
Embodiment
The present invention will be further described below in conjunction with accompanying drawing:
At first, it is embedded and replace design document to reach reference model, must keep same hierarchical structure with design when the exploitation reference model, promptly possesses same Module Division.
Then, establish the module that reference model need embed, such as A, B, C, D, E ..., and extract the interface signal of each module, set up interface document, such as, A.if, B.if, C.if, D.if, E.if ...
At last, in the reference model top layer, set up the conditional compilation code, extraction compiling parameter, such as-mA, specified modules A to embed compiling, interface document (A.if) rather than the substitution of model function code with this module when compiling compile.
The simulation run mode is constant, needn't indicate module name.
Embodiment
With the memory management module (hereinafter to be referred as MMU) in the network exchange machine chip of 24+2 is example, specifically describes the implementation detail of the verification method of this configurable interchangeable use reference model.
At first, when sub-module is set up the reference model of entire chip, guarantee that the interface of the total interface of MMU and actual module is in full accord, promptly model is consistent with the interface of prototype, so that embed and replace.Therefore need when setting up the MMU reference model, set up the interface document of .MMU.Suppose the top document MMU.rm by name of MMU reference model, so Dui Ying interface document name is made as MMU.if.rm.
After being ready to above-mentioned file, this module of MMU just possesses and can embed the condition of replacement.
Secondly, when implementing to embed proof scheme, need configuration compiling parameter, such as-m MMU, the control compiler calls the design document (MMU.dut) of MMU and the interface document (MMU.if.rm) of model.Finish in the file destination that compiling back generates and no longer comprise the code (MMU.rm) of MMU reference model, but comprised code to be measured and the corresponding reference model interface code of MMU.So just finished the foundation that module to be measured is embedded into the object code of reference model inside by configuration.
At last, invoke script operational objective code is analyzed operation result.
Other unaccounted technology (comprising hardware components) should be known technology, or is understood by those of ordinary skills.
Claims (3)
1. a verification method for configurable and replaceable reference model used by network chip comprises modeling method and configuration parameter, it is characterized in that described method comprises module to be verified is embedded in the reference model, replaces and verify module undetermined by parameter.
2. verification method for configurable and replaceable reference model used by network chip as claimed in claim 1, it is characterized in that described method comprises that also test vector is circulated into reference model by bus functional model and includes in the reference model of design module to be measured, its response resolves to analyzable textual form by bus functional model, the replacement of module is specified by the action command line parameter with configuration, compiler directive is set in code, receive the instruction of band module name, the reference model file destination of then setting up embedded this module participates in emulation.
3. verification method for configurable and replaceable reference model used by network chip as claimed in claim 1 or 2 is characterized in that described method comprises the following steps
A. by keeping same hierarchical structure with design during reference model in exploitation, promptly possess same Module Division, realize that reference model is embedded and replace design document;
B. establish the module that reference model need embed, and extract the interface signal of each module, set up interface document;
C. set up the conditional compilation code in the reference model top layer, extract the compiling parameter, the interface document substitution with this module when compiling compiles.
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101183400B (en) * | 2007-12-21 | 2011-06-15 | 威盛电子股份有限公司 | Debugging and checking method and system in graph hardware design |
| CN103150438A (en) * | 2013-03-12 | 2013-06-12 | 青岛中星微电子有限公司 | Method and device for compiling circuit |
| CN104615808A (en) * | 2015-01-19 | 2015-05-13 | 中国科学院自动化研究所 | Pre-testing hardware operational unit test method and reference model device thereof |
| CN106529099A (en) * | 2016-12-20 | 2017-03-22 | 盛科网络（苏州）有限公司 | Method for automatically generating verification model on the basis of interface |
| CN107688467A (en) * | 2016-12-23 | 2018-02-13 | 北京国睿中数科技股份有限公司 | The verification method of processor stochastic instruction multiplexing |
| CN108228973A (en) * | 2017-12-14 | 2018-06-29 | 天津津航计算技术研究所 | A kind of generation method of module interface checking assembly |
| CN112733490A (en) * | 2021-01-07 | 2021-04-30 | 苏州浪潮智能科技有限公司 | System-level verification method and system of chip and related device |
| CN113673189A (en) * | 2021-09-09 | 2021-11-19 | 杭州云合智网技术有限公司 | DUT (device under test) surrogate model based verification method, device, equipment and medium |
| CN115496034A (en) * | 2022-11-14 | 2022-12-20 | 沐曦集成电路(上海)有限公司 | Multi-mode GPU joint simulation system |
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2006
- 2006-12-29 CN CN 200610063601 patent/CN101008962A/en active Pending
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101183400B (en) * | 2007-12-21 | 2011-06-15 | 威盛电子股份有限公司 | Debugging and checking method and system in graph hardware design |
| CN103150438A (en) * | 2013-03-12 | 2013-06-12 | 青岛中星微电子有限公司 | Method and device for compiling circuit |
| CN104615808A (en) * | 2015-01-19 | 2015-05-13 | 中国科学院自动化研究所 | Pre-testing hardware operational unit test method and reference model device thereof |
| CN104615808B (en) * | 2015-01-19 | 2018-07-03 | 北京思朗科技有限责任公司 | A kind of test method and reference model device of hardware computation component to be tested |
| CN106529099A (en) * | 2016-12-20 | 2017-03-22 | 盛科网络（苏州）有限公司 | Method for automatically generating verification model on the basis of interface |
| CN107688467A (en) * | 2016-12-23 | 2018-02-13 | 北京国睿中数科技股份有限公司 | The verification method of processor stochastic instruction multiplexing |
| CN107688467B (en) * | 2016-12-23 | 2019-11-15 | 北京国睿中数科技股份有限公司 | The verification method of processor stochastic instruction multiplexing |
| CN108228973A (en) * | 2017-12-14 | 2018-06-29 | 天津津航计算技术研究所 | A kind of generation method of module interface checking assembly |
| CN112733490A (en) * | 2021-01-07 | 2021-04-30 | 苏州浪潮智能科技有限公司 | System-level verification method and system of chip and related device |
| CN113673189A (en) * | 2021-09-09 | 2021-11-19 | 杭州云合智网技术有限公司 | DUT (device under test) surrogate model based verification method, device, equipment and medium |
| CN115496034A (en) * | 2022-11-14 | 2022-12-20 | 沐曦集成电路(上海)有限公司 | Multi-mode GPU joint simulation system |
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