JPS6250858B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention provides a pseudo-failure setting processing method, in particular, provides an instruction to perform scan-in/scan-out for a latch (LATCH) of a data processing device as a diagnostic instruction, and The present invention relates to a pseudo-fault setting processing method that allows pseudo-faults to be generated by diagnostic commands and completely automates pseudo-fault tests.

(2) Technical background and issues In general, in order to improve the reliability of large-scale data processing systems, in addition to testing normal operation, it is necessary to forcibly generate equipment failures. Tests are also being conducted to determine whether failure handling is performed correctly. That is, through failure testing, it is determined whether failures in the equipment are correctly detected and processes corresponding to the failure situation are correctly executed, and debugging of hardware and software failure handling is performed.

In order to conduct a failure test, it is necessary to create various failure situations by some means, but it is difficult to actually test by incorporating failure devices that correspond to various failure types into the system. This is not realistically possible, and it is not easy to set up the desired failure environment.

Conventionally, failure tests have been conducted by generating pseudo-failures that appear to be failures, although they are not actual failures, in the following manner. To stop a data processing device at an appropriate point while the data processing device is executing an instruction. Then, with the clock stopped, the latch of the data processing device is manually scanned in/scanned out, and then the data processing device is released from the stop state and started. An abnormality in the latch will result in the recognition that a failure has occurred.

However, the conventional method described above has the disadvantage that the test takes a very long time because a pseudo fault is generated by manual operation. In addition, when operational errors are likely to occur and fault handling is not executed correctly, it is necessary to determine whether the cause is due to a hardware or software bug or an operational error, and the same test must be repeated multiple times. It was necessary to repeat it. Further, there was a problem in that it was difficult to control the latch at the appropriate timing for testing, making it impossible to conduct a complete test.

(3) Object and Structure of the Invention The present invention aims to solve the above-mentioned problems, and enables a data processing device to freely control its own various latches at an appropriate timing using diagnostic commands, thereby eliminating manual operations. , which aims to enable full automation of simulated failure tests. Therefore, the pseudo failure setting processing method of the present invention is applicable to a data processing system that includes a data processing device and a service processor that monitors, operates, and controls the system via a system console interface. ,
A diagnostic instruction that requests the service processor to perform scan-in/scan-out processing for various latches, wherein the operand portion of the diagnostic instruction specifies at least the processing content for the target latch and the multiple scan addresses regarding the target latch. The service processor includes a diagnostic instruction execution means for executing a diagnostic instruction specifying a scan control information area in which information is stored, and the service processor executes the scan control information specified by the operand section in response to a processing request based on the diagnostic instruction. The system includes a diagnostic command processing means that refers to the area and executes scan-in/scan-out for specified multiple latches according to the specified processing content, and executes the above diagnostic command to target multiple latches. It is characterized by the ability to generate pseudo failures.

This will be explained with reference to the drawings below.

(4) Embodiments of the Invention FIG. 1 shows the configuration of an embodiment of the present invention, FIG. 2 is an explanatory diagram of an example format of a scan-in command, FIGS. 3 to 6 are explanatory diagrams of a scan control information area, and FIG.
The figure shows a format example of a scan-out command, and FIG. 8 shows an explanatory diagram of a scan control information area for scan-out.

In the figure, 1 is the central processing unit (CPU), 2 is the memory, 3 is the system console interface, and 4
is a service processor (SVP), 5 is an instruction register, 6 is a working address register, 7 is a decoder, 8 is a result register, 9 is a diagnostic instruction, 1
0 is a scan control information area, 11 is a scan address register, 12 and 13 are scan out result storage areas, 14 is an output data register,
15 represents a select address register.

The central processing unit 1 is a device that sequentially fetches and executes instructions stored in a memory 2. memory 2
The instructions read from the CPU are stored in the instruction register 5, analyzed and executed by the decoder 7, but not all instructions are executed by the central processing unit 1. 9, the service processor 4 is requested to perform the process. The system console interface 3 is an interface between the central processing unit 1 and the service processor 4 for controlling the operation of the system. The service processor 4 is a subsystem that includes a processor independent of the central processing unit 1, and is capable of monitoring, operating, and controlling the system all at once via the system console interface 3. It's summery.

As the diagnostic command 9 according to the present invention, for example, a scan-in command 9-1 as shown in FIG. 2 and a scan-out command 9-2 as shown in FIG. 7 are prepared.

A hexadecimal number (83) is assigned to the operation code of the first byte of the scan-in instruction 9-1, indicating that it is a general diagnostic (DIAGNOSE) instruction. A hexadecimal number (C2) is given as a sub-operation code in the subsequent second byte, indicating that this is an instruction to scan in a latch. In the operand section, scan control information area 1 is determined by the contents of base register _B2 and displacement _D2 .
It is made to indicate a real address of 0.

The scan control information 10 for scan-in is configured, for example, as shown in FIG. 3, and indicates information regarding the latch to be processed and the content of the process. The first word SCW is a scan control word and has the content as shown in FIG. 4, for example. In Figure 4, the first byte of SCW
The OPC indicates detailed control instructions such as scan-in timing, and the following control is performed depending on the value.

(i) When OPC is "0" This indicates no operation and scan-in is not executed.

(ii) When OPC is "1" Scan-in continues to the latch specified by SAW, which will be described later. Here, continuing means that the contents of the scanned-in latch are not changed until the scan-in is canceled. Scan-in is started before the end of the diagnostic instruction. The release is performed either by the hardware due to the occurrence of a machine check or by a time monitoring check of the system console interface 3, for example of about 1 second.

(iii) When OPC is "2" Scan-in starts after the diagnostic command is completed. The rest is the same as when OPC is "1".

(iv) When OPC is "3" For the latch specified by SAW, as described below.
If the SID bit is "1", scan-in is performed; if it is "0", scan-in is not performed.
In this operation, scan-in occurs with the clock stopped.

(v) When OPC is "4" With the hardware scan reset,
Scans out the latch specified in SAW to the area specified in DAW (described later). A scan-reset latch is scanned back in to its original value after being scanned out. In this operation, scan-in occurs with the clock stopped.

(vi) When OPC is "5" With the hardware scan reset,
For the latch specified by SAW, if the SID bit is "1", scan-in is performed so that the value is reversed to the original value, and if the SID bit is "0", scan-in is performed to the original value. After scanning in, the latch specified in SAW is scanned out to the area specified in DAW. In this operation, scan-in occurs with the clock stopped.

Note that OPC codes other than the above are, for example, undefined.

The UNIT part of the SCW specifies the device in which the latch to be scanned in exists. Central processing unit (CPU), memory control unit (MCU),
Two bits are allocated to each channel device (CHP), and device numbers from 0 to 3 can be specified.

SBC is a scan bit counter and indicates the number of bits to be scanned in or scanned out. This is equal to the number of words in SAW.

DAW shown in FIG. 3 is a data address word, and indicates the actual address of the area where scan-out data is stored, as shown in FIG. The scanout data is stored left-justified in binary in the order specified in the SAW. For missing bits in the last word,
“0” is stored.

SAW is a scan address word, and is configured as shown in FIG. 6, for example. of the first bit
The SID is a scan-in data bit, and is used, for example, to control whether or not to scan-in. The scan address from the 7th bit to the 31st bit indicates the address of a latch that is determined to be able to be handled by the service processor 4.

The scanout command 9-2 has a format as shown in FIG. 7, for example. Scan-in instruction 9-1 shown in Figure 2 except that hexadecimal number (C3) is assigned as the sub-operation code.
The same is true for the scan control information area 10, as shown in FIG. 8, which is similar to the scan control information area used in the scan-in command 9-1. The result of scanout is
It will be stored in the scan data storage area pointed to by the DAW.

For example, when a diagnostic command 9 such as the above-mentioned scan-in command 9-1 appears, the central processing unit 1 processes as follows. First, the diagnostic instructions 9 are sequentially issued from the memory 2 and set in the instruction register 5, and the decoder 7 decodes the operation code.
Via the system console interface 3,
The service processor 4 is notified that the diagnostic command 9 has been received. Further, the address specified in the operand section is calculated by an operand address calculation circuit (not shown) and stored in the working address register 6. The service processor 4 has a diagnostic command 9
When notified, it instructs the system console interface 3 to scan out the sub-operation code and working address register 6, and reads them out to the scan-out result storage area 12, which is a storage area of the service processor 4. The contents of the working address register 6 indicate the address of the scan control information area 10 of the memory 2. next,
This address is transferred to the central processing unit 1 via the system console interface 3. The central processing unit 1 stores the scan control information area 10 in the memory 2.
The control information is extracted from and written into the result register 8. System console interface 3
scans out this result register 8 and passes the result to the scan-out result storage area 13 of the service processor 4. Service processor 4
Based on that, if the diagnostic instruction 9 is a scan-in instruction 9-1, it writes the output data to the output data register 14 at the specified timing, and also writes the output data to the select address register 1.
Set the scan address to 5. The contents of this select address register 15 are transferred to the scan address register 11. The system console interface 3 stops the clock of the central processing unit 1, transfers a scan address and a scan-in signal to the central processing unit 1, and performs a scan-in. This scan-in continues until an error such as a machine check occurs due to forced scan-in of the latch, or until one second elapses.

Similarly, in the case of scan out, the contents of the latch having the scan address indicated by the scan address register 11 are stored in the area indicated by the DAW in the scan control information area 10 of the memory 2.

In this way, the diagnostic command 9 allows scan-in and scan-out to any latch with the clock of the central processing unit 1 temporarily stopped.
It will be processed independently from normal processing instructions. Therefore, by preparing the diagnostic command 9 at an appropriate location, it is possible to automatically generate a pseudo failure, and it is also possible to collect information regarding the latch state after the failure occurs.

(5) Effects of the Invention As explained above, according to the present invention, when performing a simulated failure test, there is no need to generate a simulated failure manually, and the simulated failure test can be completely automated and accurately performed. And rapid testing becomes possible. In particular, the present invention uses diagnostic instructions to cause the service processor, system console interface, to intervene and temporarily stop the central processing unit clock to read the scan address indicated by the scan address word (SAW). When a group of flip-flops is scanned in, it is possible to make it appear as if a pseudo failure has occurred at the same time when the central processing unit is activated. can be verified at the same time. Settings for multiple flip-flops can be made freely, and multiple pseudo faults can be generated at the same time at any timing without being aware of the values.

[Brief explanation of the drawing]

FIG. 1 shows the configuration of an embodiment of the present invention, FIG. 2 is an explanatory diagram of an example format of a scan-in command, FIGS. 3 to 6 are explanatory diagrams of a scan control information area, and FIG.
The figure shows a format example of a scan-out command, and FIG. 8 shows an explanatory diagram of a scan control information area for scan-out. In the figure, 1 is a central processing unit, 2 is a memory, 3 is a system console interface, 4 is a service processor, 5 is an instruction register, 9 is a diagnostic instruction,
10 represents a scan control information area.

Claims (1)

[Scope of Claims] 1. In a data processing system comprising a data processing device and a service processor that monitors, operates, and controls the system via a system console interface, the data processing device is a diagnostic instruction that requests scan-in/scan-out processing for various latches, and the operand part of the diagnostic instruction stores at least the processing contents for the target latch and a plurality of scan address information regarding the target latch. The service processor includes a diagnostic instruction execution means for executing a diagnostic instruction specifying a scan control information area specified by the service processor, and the service processor refers to the scan control information area specified by the operand section in response to a processing request based on the diagnostic instruction. The system is equipped with a diagnostic instruction processing means that executes scan-in/scan-out for specified multiple latches according to specified processing contents, and by executing the above-mentioned diagnostic instructions, it is possible to detect pseudo failures targeting multiple latches. A pseudo-failure setting processing method is characterized in that it can occur.