JPH05101697A - Fault diagnostic circuit for lsi - Google Patents

Abstract

PURPOSE:To provide the fault diagnostic circuit which diagnoses the operation of a RAM or a register file in an LSI, which has the RAM or the register file and is built in a device, without reducing the clock frequency for normal operation. CONSTITUTION:A pattern generation mode register 20 which is controlled by the control instruction outputted from a diagnostic processor 2 in the device to be diagnosed and holds and outputs a designated pattern and a test frequency register 21 which holds and outputs the frequency in test corresponding to the instruction from the diagnostic processor 2 are provided in LSIs 30 to 32 with RAMs. A pattern generating circuit 12 which outputs the address value in a RAM 16, the value to be stored in the address designated by this address value, and an expected value to be read out from the RAM 16 in accordance with outputs of these registers and an expected value collating circuit 18 which compares the value read out from the RAM 16 and the expected value with each other are provided in LSIs 30 to 32, and the RAM is diagnosed by the output result of this expected value collating circuit 18.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an LSI failure diagnosis circuit, and more particularly to an LSI incorporated in an information processing device such as a computer, in which an LS including a RAM (random access memory) or an RF (register file).
The present invention relates to an LSI failure diagnosis circuit used when determining whether the above-mentioned RAM or RF in I operates normally.

[0002]

2. Description of the Related Art Conventionally, there are two types of failure diagnosis circuits for an LSI incorporated in an apparatus such as an information processing apparatus. The first circuit executes a diagnostic program on a diagnostic processor incorporated in the above-mentioned device in a diagnostic mode in which the above-mentioned device is operated at a clock called a diagnostic clock which is considerably slower than the clock for normal operation in which the normal device operates. It is what is executed. The diagnostic program first makes initial settings necessary for diagnosis on the device to be diagnosed. Next, the diagnostic data is set to the F / F necessary for the diagnosis through the path called F / F (flip-flop) group called the scan path. Next, a diagnostic clock is applied, the data required for diagnostics is read in the scan path, and the expected value is checked on the diagnostic processor. Further, when the collation result does not match the expected value, the LSI diagnostic data automatically indexes the suspicious LSI by indexing information that describes the correspondence between the diagnostic data called the fault dictionary and the faulty LSI. For example, a program for diagnosing whether the parity error detection circuit is operating normally sets a value to a predetermined F / F so as to generate a parity error, and then advances the clock, Check that the F / F indicating that this parity error has occurred is set. If it is different from the expected value, the LSI in which this parity check circuit exists is pointed out as the faulty LSI.

FIG. 5 is a flow chart for explaining the operation of the above-mentioned first circuit. All the programs that execute the operation of the first circuit are executed by the above-mentioned diagnostic processor. First, the device to be diagnosed is initialized by clearing the F / F by the scan path of the device to be diagnosed (step S1), and then diagnostic data is set by the scan path (step S2). After that, the diagnostic clock is advanced by a required amount (step S3), and the data required for diagnosis is read by the scan path (step S3).
4). If the read data does not match the expected value (steps S5 and S6), the failure dictionary is indexed (step S7) and the failed LSI is displayed on the operation screen (step S8). A conventional second circuit of this type normally tests the function of the instruction set of the device itself at the clock at which the device under test operates. The software visible register or memory of the device under test is used as an observation point, and the diagnostic data is set at the observation point as described above, and the test is performed by the instruction set of the device itself by starting from the diagnostic processor. The program is executed, the data at the observation point is read by the diagnostic processor, collated with the expected value, and the diagnostic processor reads a flag for detecting a parity error or the like and indexes the fault dictionary by pointing out the fault dictionary.

FIG. 6 is a flow chart for explaining the operation of this second circuit. First, create a test program created manually or by an instruction set of the device under test generated with random numbers, and diagnostic data for executing this test program, and load it into the memory of the device under diagnosis via the diagnostic processor. After that (step S10), the diagnostic processor instructs the device under diagnosis to execute the test program (step S11). The diagnostic processor receives the test program execution completion report from the device under test, reads the diagnostic data from the software register or memory of the device under test (step S12), and outputs the expected value generated by the software simulator of the device under test. (Step S13), and if they do not match, the result is displayed on the screen of the console of the above-mentioned device (step S13).
14) Furthermore, the diagnostic processor reads the error detection flag and indexes the failure dictionary (step S15) to find the failure L.
The SI is pointed out (step S16). On the other hand, when a failure occurs not only in the LSI but also in a unit in the device,
Time during which the system is down by logically disconnecting the faulty unit or one of the same systems that exist multiple times in that unit and operating the system without temporarily using it There is a method called “degrade” that shortens as much as possible. When performing a degradation, the diagnostic processor is used to isolate the part where the failure has occurred, or the diagnostic processor and the device under test cooperate with each other, and in the latter case, without bringing down the system during system operation, There is also a method of automatically disconnecting the failure occurrence unit. For example, if you connect multiple processors, usually all perform the same processing, collate the results, and if there is a discrepancy in the results, the majority vote is taken and the result issued by the minority processor is incorrect. There is a fault-tolerant system in which the resulting processor determines that it has failed and automatically degrades.

[0005]

In the above-mentioned first circuit of the conventional method, since the observation point of the diagnostic data can be set at a fine level of F / F, which LSI includes the circuit to be diagnosed. Since it is known, the fault dictionary of the LSI is indexed from the diagnostic data and the fault L
It is possible to wash out SI.

However, since it is necessary to perform diagnosis using a diagnostic clock, which is a very slow clock with respect to the normal operation clock, there is a drawback in that a failure that occurs only during the normal operation clock cannot be detected. The reason why the diagnostic clock has to be used is that unless the diagnostic clock is stepped once, the diagnostic range is widened and the faulty LSI cannot be indicated from the F / F diagnostic data.

Another disadvantage is that the diagnostic clock is slow and the diagnostic program execution time is too long to ignore because the scan path frequently reads and writes data to the F / F. Especially, it takes a huge amount of time to diagnose the RAM and the RF by the diagnostic clock.

On the other hand, since the conventional second circuit of this type operates with the normal operation clock, the execution time is short, and the function of the instruction of the device under test is tested with the normal operation clock. Therefore, it is possible to diagnose in the normal operating environment, and since the function test of the instruction of the device to be diagnosed is performed, the OS (operating system) running on the device to be diagnosed or the application program is for the time being. It is very practical as a test necessary for operation, and it is also possible for the diagnostic processor to read an error report flag such as error detection in the parity check and to index the fault dictionary by pointing out the fault dictionary. However, for example, the RA existing in the LSI
Since the test is not performed for all the addresses of M and RF, there is a possibility that the failure of the LSI holding these will be missed.

By the way, in the device actually shipped, the part with the highest failure rate is where switching frequently occurs in the digital circuit, and that part is the data system part.
That is, the data path around the arithmetic circuit or the storage element, or the storage element itself. Precise diagnosis of these parts with high failure rates is impossible with the above two conventional circuits. This is because, in the case of the first circuit, the diagnostic clock is a prerequisite, so that the diagnostic environment is far from the reality, and in terms of the execution speed of the diagnostic program, for example, when diagnosing the RAM, the previous address Reading and writing tests take a very long time and are unrealistic. In the case of the second circuit, since it is a function test of the test instruction, a sufficient test cannot be performed on the RAM.

As described above, since the conventional diagnostic circuit of this type does not perform detailed diagnosis, or is performed far from the normal environment, there is a possibility that a failure may be overlooked and the unit to be degraded cannot be degraded. On the other hand, on the contrary, since it is not possible to narrow down the location of the failure sufficiently, the parts that do not need to be upgraded will be degraded.
There is a drawback that the performance of the system is unnecessarily reduced.

[0011]

A failure diagnosis circuit for an LSI according to the present invention comprises an LSI having at least one of a random access memory and a register file therein and incorporated in an apparatus, and a diagnostic processor for the apparatus. Targeting the LSI provided in the information processing device
In the failure diagnosis circuit for use, the diagnostic processor outputs a command for writing and reading data via the flip-flop of the scan path, and also relates to the start and stop of the clock other than the time of the failure diagnosis and the progress of the clock at the time of the diagnosis. An address register having a function of outputting an instruction and designating an address corresponding to the address signal to the random access memory or the register file when an address signal is applied, and the write signal when a write signal is received A write register for writing the value specified by in the address specified by the address register, and a read register for temporarily storing a value output by the random access memory in the LSI or the register file and outputting it as a read signal to the outside. The L
A value to be given to the address register and the write register for the random access memory or the register file is sequentially stored as a pattern in response to a data writing and reading command of the diagnostic processor provided in the SI and by an instruction related to the step at the time of the diagnostic. The pattern generation mode register that outputs these values in response to the step-related instruction, the address value to be given to the address register according to the output from the pattern generation mode register, and the address specified by the address value The value to be stored is output to the write data register, the expected value output from the read data register provided in the LSI is generated and output, and the test ends when a series of tests is completed by the pattern. signal A pattern generating circuit output is, with the expected value provided in said LSI said read data
A test is performed when the expected value does not match the value read by the register file while comparing the value read by the register with the value in the random access memory in the LSI or the register file and outputting the result. An expected value matching circuit for outputting an end signal, and the L
A test result flag which is provided in the SI and stores the output of the collation result from the expected value collating circuit; and a test end flag which is provided in the LSI and sets a flag indicating a test end when the test end signal is received. It is configured to include a circuit including the following.

[0012]

1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram showing an embodiment of a test circuit provided inside each of the LSIs 30 to 32 with RAM.

L with RAM (random access memory)
SIs 30 to 32 are the test instruction controller 1 and the signal line 130.
To 132 respectively. Since the test instruction control unit 1 performs write control on the pattern generation mode register 20 and the test count register 21 held by the test circuits inside the LSIs 30 to 32 with RAM, information is output from the signal lines 130 to 132. Send out. The diagnostic processor 2 uses the signal lines 302, 312, 32.
2 distributes the clock to the RAM-equipped registers 30 to 32, and when the clock is stopped, R
F / from the LSIs 30 to 32 with AM via the scan path
Reads and writes data in F (flip-flop). The test instruction control unit 1 exists in the device to be diagnosed, and includes the pattern generation mode register 2 in the LSIs 30 to 32 with RAM.
0 and an access instruction of the test count register 21 and a test request interrupt to the diagnostic processor 2 are sent, and an instruction to restart the execution by receiving the test end interrupt from the diagnostic processor 2 is controlled. And 201 transmit and receive an interrupt signal to and from the diagnostic processor 2. Hereinafter, the test circuit included in the LSI 30 with RAM shown in FIG. 1 will be described. The test circuits in the other LSIs with RAM 30 and 31 are also the same. The test circuit control unit 11 has a test mode flag 1 that holds information indicating that the test mode is in the test mode.
9. A pattern generation mode register 20 for storing information indicating what kind of pattern is generated and a test is performed,
Test count register 2 to specify the number of test repetitions
1, test end flag 2 indicating that the test is completed
2. A test result flag 23 indicating a test result is held, connected to the test instruction control unit 1 in FIG. 1 by the signal line 130, and accessed by the test instruction control unit 1. The clock control circuit 13 includes a signal line 301,
332, 304, 305, 306, 307, and 308 control units in the test circuit and RAM and a write data register (WDR) 15 of the RAM, an address register (ADR) 14, and a read data register (RDR) 1.
7, the clock sent from the diagnostic processor 2 is stabilized by the signal line 302 and provided. The pattern generation circuit 12 sends the address and the test data to the signal lines 204 and 205 while observing the value of the pattern generation mode register 20 by the activation of the test circuit control unit 11, and the expected value of the read data. Signal line 208
To the expected value matching circuit 18 via. The expected value comparison circuit 18 compares the data sent via the signal lines 208 and 708 and outputs the result to the test circuit control unit 11 via the signal line 801. The test circuit control unit 11 looks at the test result through the signal line 801, and if a mismatch with the expected value occurs, sets the test end flag 22 (for example, sets the logical value to “1”) to indicate that the test has ended. The test result flag 23 is set to indicate that a failure has occurred. When the test according to one pattern is completed, the test end flag 22 is set ("1") to indicate the end of the test. If the value of the test count register 21 is 2 or more, the same test is performed again. Run the test.

Next, the pattern generation mode register 20
The test count register 21 will be described. The test count register 21 is a register for designating the number of tests and is R
It is a register used to detect a failure such as an intermittent failure by repeating the same test after all the tests for AM16 are completed, and specify how many times the test is repeated in consideration of the diagnostic time. It is a register for doing. The pattern generation mode register 20 specifies a random pattern, a pattern that is generated by shifting 1 or a pattern that alternately generates 1 and 0 to be used for the test. Register.

Next, the pattern generation mode register 20 and the test count register 21 will be described. The test count register 21 is a register for designating the number of tests and is a RAM.
It is a register used to detect a failure such as an intermittent failure by repeating the same test after the test for 16 is completed, and specifies how many times the test is repeated in consideration of the diagnostic time. It is a register for doing. The pattern generation mode register 20 is a random
This register is used to specify which pattern is to be used for the test, such as a pattern generated by shifting the pattern 1, or a pattern in which 1 and 0 alternate.

FIG. 3 is a flow chart for explaining the operation of the LSI fault diagnosis circuit of the present invention shown in FIG. The operation example shown in the flowchart of FIG. 3 is an example of performing diagnosis by executing a diagnostic program from the diagnostic processor 2. First, the diagnostic processor 2 includes the LSIs 30 to 32 with RAM.
The test circuit is initialized by setting each test mode flag 19 of (1) and resetting the test end at the same time (step S20). Next, the test execution mode, the test execution mode, and the test repeat count are designated in the pattern generation mode register 20 and the test count register 21, respectively. (Step S21). For example, the same test is repeatedly performed to set the number of times of repetition for finding a fault close to an intermittent fault, and to specify whether to randomly generate a pattern.

When the test mode flag 19 is set (for example, in the state of "1"), the LSI with RAM is in a state where it does not receive a signal from the power supply route during normal operation.

Next, the diagnostic processor 2 supplies a clock for normal operation (step S22). After a suitable time, if the content of the test end flag 22 is, for example, "1", the normal clock is stopped (steps S23 and S24), the content of the test result flag 23 is read (step S25), and the content of the test result flag 23 is read. From this test result flag 2
When a failure of the RAM-equipped LSI having No. 3 is detected, a failure dictionary (not shown) is indexed to find the faulty RAM-equipped L.
The SI is displayed on a console screen (not shown) (steps S26 to S28).

FIG. 4 is a flow chart showing the operation of the diagnostic apparatus of the present invention shown in FIG. 1 as an example in which the diagnostic processing apparatus is activated by the instruction of the apparatus to be diagnosed. First, the test command controller 1 in the device to be diagnosed shown in FIG.
An instruction for setting a value is executed in the register 20 and the test circuit register 21 to set what test should be executed (step S30). Next, the test instruction control unit
The ST / ACT instruction is executed (step S31), the diagnostic processor 2 is interrupted, and the diagnostic processor 2
Start the diagnostic program of. After that, the device to be diagnosed
Until the diagnosis end report is received from the diagnosis processor 2, the instruction is not executed and the waiting state is entered.

On the other hand, the diagnostic processor 2 first stops the normal working clock of the device to be diagnosed (step S3).
2) The test mode flag 19 in the LSI with RAM is set (step S33). After that, the normal operation clock is started again (step S34), and the tests of the LSIs 30 to 32 with RAM of the device to be diagnosed are executed. After a lapse of an appropriate time, the normal operation clock is stopped (step S35), the test end flag 22 of the LSI with RAM is checked (step 36), it is confirmed that the test is completed, and the content of the test result flag 23 is checked. Read on scan path (step S37), L with RAM
If a failure occurs in SI, the failure dictionary desired to be shown is indexed, and the operation terminal (not shown) is given a failure LS.
I is displayed (step S38). After that, the normal operation clock of the device to be diagnosed is started (step S3
9), TEST / END instruction is executed to restart the execution of the device under diagnosis in the waiting state.

The device to be diagnosed whose execution has been restarted is L with RAM.
Read the contents of the SI test result flag (step S
41). For example, based on the result, the device under test enhances self-diagnosis by increasing the frequency of the above processing,
Normal processing can also be performed.

In the above-described embodiments, the description has been given for the LSI with RAM, but an LSI using RF instead of the RAM 16 in FIG. Obviously it can be used.

[0023]

EFFECT OF THE INVENTION Since the RAM and RF LSI can be finely diagnosed at high speed with the clock for normal operation, the following effects can be obtained.

That is, since the fine diagnosis can be performed by the normal operation clock, the diagnosis time can be shortened.

Further, since the faulty LSI with RAM and RF can be pointed out accurately on the actual machine, it is possible to reduce the lead time of the work when a fault occurs at the shipping destination.
It is possible to reduce the possibility of overlooking a failure at the time of automatic degrading during system operation, and to minimize the conic to be degraded.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an LSI failure diagnosis circuit of the present invention.

FIG. 2 is a block diagram showing an embodiment of a test circuit provided in the LSI with RAM shown in FIG.

FIG. 3 is a flowchart showing an example of the operation of the failure diagnosis circuit for LSI shown in FIG.

4 is a flowchart showing an example of an operation of the failure diagnosis circuit for LSI shown in FIG. 1, which is different from that in FIG.

FIG. 5 is a flowchart showing an operation of an example of a conventional diagnostic circuit of this type.

FIG. 6 is a flow chart showing an example of a conventional diagnostic circuit of this type different from that of FIG.

[Explanation of symbols]

 1 Test Command Control Unit 2 Diagnostic Processor 11 Test Circuit Control Unit 12 Pattern Generation Circuit 13 Clock Control Circuit 16 RAM 18 Expected Value Matching Circuit 19 Test Mode Flag 20 Pattern Invention Mode Register 21 Test Count Register 22 Test End Flag 23 Test Result Flag 30 to 32 LSI with RAM

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical display location G06F 11/22 350 9072-5B 360 P 9072-5B

Claims (4)

[Claims] 1. An L for an LSI provided in an information processing apparatus that includes at least one of a random access memory and a register file and is incorporated in an apparatus, and the processor for diagnosis of the apparatus.
In the SI failure diagnosis circuit, the diagnosis processor outputs an instruction to write and read data via a flip-flop of a scan path, and starts and stops a clock other than at the time of failure diagnosis and advances the clock at the time of diagnosis. Address register for designating an address corresponding to the address signal to the random access memory or the register file when an address signal is applied, and the writing when a write signal is received. A write register for writing a value specified by a signal into an address specified by the address register, and a read register for temporarily storing a value output by the random access memory in the LSI or the register file and outputting it as a read signal to the outside. Provided in the LSI In response to the data writing and reading commands of the diagnostic processor, and in accordance with the step instruction at the time of diagnosis, the values to be given to the address register and the write register for the random access memory or the register file are sequentially stored as a pattern and the step is performed. A pattern generation mode register for outputting these values in accordance with an instruction regarding
An address value to be given to the address register according to an output from the register and a value to be stored at an address designated by the address value are output to the write data register and read data provided in the LSI. A pattern generation circuit that generates and outputs an expected value output from a register and outputs a test end signal when a series of tests is completed by the pattern,
The expected value provided in the LSI and the value in the random access memory or the register file in the LSI read by the read data register are compared, the result is output, and the expected value and the An expected value collating circuit that outputs a test end signal when the values read in the register file do not match, and a test result flag that stores the collation result output from the expected value collating circuit provided in the LSI. , The LS
A fault signal circuit for an LSI, comprising a circuit provided in I and comprising a test end flag for setting a flag indicating the end of the test when the test end signal is received. 2. An L for an LSI provided in an information processing apparatus having at least one of a random access memory and a register file built in a device and a diagnostic processor for the device.
In the SI failure diagnosis circuit, the diagnosis processor outputs an instruction to write and read data via a flip-flop of a scan path, and starts and stops a clock other than at the time of failure diagnosis and advances the clock at the time of diagnosis. Address register for designating an address corresponding to the address signal to the random access memory or the register file when an address signal is applied, and the writing when a write signal is received. A write register for writing a value specified by a signal into an address specified by the address register, and a read register for temporarily storing a value output by the random access memory in the LSI or the register file and outputting it as a read signal to the outside. Provided in the LSI Is a test count register for storing the number of times of tests repeated in response to an instruction output from said diagnostic processor through the scan path, wherein L
A value to be given to the address register and the write register for the random access memory or the register file is sequentially stored as a pattern in response to a data writing and reading command of the diagnostic processor provided in the SI and by an instruction related to the step at the time of the diagnostic. The pattern generation mode register that outputs these values in response to the step-related instruction, the address value to be given to the address register according to the output from the pattern generation mode register, and the address specified by the address value A value to be stored is output to the write data register, an expected value output from a read data register provided in the LSI is generated and output, and a series of tests based on the pattern is stored in the test count register. three Then, the pattern generation circuit that terminates the operation and outputs the test end signal when the test is executed the number of times stored in the test count register, and is read by the expected value and the read data register provided in the LSI. The value in the random access memory in the LSI or the value in the register file is compared and the result is output, and a test end signal is output when the expected value and the value read in the register file do not match. An expected value collating circuit, a test result flag provided in the LSI for storing the output of the collation result from the expected value collating circuit, and provided in the LSI to indicate the end of the test when the test end signal is received. Fault diagnosis for LSI, characterized by comprising a circuit consisting of a test end flag for raising a flag Road. 3. A diagnostic processor, which is provided in a device having the LSI, outputs an instruction for designating a pattern value for the pattern mode generation / register via a scan path and outputs a signal for activating the diagnostic processor. A test instruction control unit that starts up and outputs an instruction for stepping up by the diagnostic processor, and when the operation of the diagnostic processor is completed, performs control to hold the device in a waiting state until an interrupt signal from the diagnostic processor is received. The fault signal circuit for LSI according to claim 1, which has. 4. An instruction for designating a pattern value for the pattern mode generation / register and an instruction for designating the number of tests, which are provided in a device having the LSI, are output through a scan path and the diagnostic processor is activated. A signal that causes the diagnostic processor to be activated, the diagnostic processor to output an instruction for stepping, and when the operation of the diagnostic processor is completed, the device is placed in a waiting state until an interrupt signal is received from the diagnostic processor. 3. The failure diagnosis circuit for LSI according to claim 2, further comprising a test instruction control unit that performs a holding control.