JPH0255815B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] In a channel processor that commonly controls a plurality of channels, the common part and the individual parts are provided with appropriate fault handling and processing corresponding to the fault state in each.
Enables reporting to the CPU and collection of detailed failure information by SVP.

[Industrial Application Field] The present invention relates to a computer system,
In particular, it relates to a channel fault handling method in a channel processor.

[Conventional technology]

FIG. 2 shows the configuration of a general computer system having a channel processor, which is the object of the present invention. In the figure, 1 is the main memory
MSU, 2 represents a central processing unit CPU, 3 represents a channel processor CHP, 4 represents a channel CH, 5 represents an input/output device I/O, and 6 represents a channel processor SVP.

Channel Processor CHP supports multiple channels
The CHs are sequentially controlled to perform input/output data transfer between the input/output device I/O and the main storage device MSU.

The channel processor CHP consists of an individual section that controls each channel CH individually and cyclically, and a
It includes a common part that sequentially processes processing requests generated on the CH, and manages each failure. When a failure occurs, it is reported to the operating system (OS) of the central processing unit CPU, and detailed information about the failure is collected by the service processor SVP.

FIG. 3 shows the control mechanism of the channel CH in the channel processor CHP. In the figure, 7 is the 16 channels CH0 to CHF
A stack memory in which respective control information is stored, 8 indicates an individual section, and 9 indicates a common section.

In the individual section 8, from the stack memory 7, channels CH0 to CH1, CH2, ..., CHF, CH0,
Control information is read and updated cyclically like CH1, CH2, . . . At this time, if processing is required by the common unit 9, a processing request is issued to the common unit 9.

At this time, if the common unit 9 is processing a processing request from another channel, it issues the processing request again in the next cycle. Once the request is accepted,
The common unit 9 reads out the control information of the channel, processes it, and updates it.

By the way, during the above operation, a hardware failure occurred.
For example, if a register parity error occurs, the channel control check will notify you of this.
Reported to the OS as a CCC (Channel Control Check).

For example, if the common section 9 is composed of a microprocessor and a 2-bit error is detected in its control memory, this is reported to the OS as channel damage, indicating that it is impossible to continue processing.

Additionally, a common method is for failures that occur multiple times during the processing of these failure reports to be notified to the OS as channel damage, and for the OS to perform failure recovery processing.

In addition, if a failure occurs to the extent that normal operation can continue while a certain channel is operating, only that channel will undergo a channel control check (CCC).
Therefore, it is common to allow other channels to continue normal operation without being affected.

For this reason, in the conventional method, during recovery processing by the OS, log information (hereinafter referred to as logout information) records the minimum necessary amount of failure status in each individual section of each channel so that processing execution of unrelated channels is not affected. It created a storage area, reported failures to the CPU, and output logout information to the main storage MSU.

There was also a conventional system that outputs logout information to the service processor SVP.
In such a system, it is necessary to temporarily store logout information for the SVP in a storage area called a log buffer within the CHP.

Figure 4 shows an example of a channel failure handling mechanism in a conventional computer system. In the figure, 1 is the main storage unit MSU, 2 is the central processing unit CPU,
3 is the channel processor CHP, 4 is the channel
CH, 5 is the input/output device I/O, 6 is the service processor SVP, 8 is the individual part, 9 is the common part, 10 is the status register, 11 is the operating system
OS, 12 is an error detection latch EDL, and 13 and 14 are logout information.

A plurality of error detection latches EDL are provided for each channel CH, and are used to display the position of a register or the like where a failure such as a parity error has occurred.

The logout information 13 is provided to indicate the failure occurrence status for each channel CH, and is provided to indicate the failure occurrence status for each channel CH.
It is created by consolidating EDL information and converting it into a simple code. This logout information 13 is stored in the control information area for each channel.

The logout information 14 is for indicating the failure occurrence state within the common section 9.

The common unit 9 performs fault processing based on this logout information, and sets a channel control check CCC (in the case of a minor fault) or channel damage CD (in the case of a severe fault) in the status register 10 depending on the fault. and central processing unit
Report to CPU OS. Channel damage is also reported to the service processor SVP, which
Logout information to service processor SVP 13,
14 is read out and the cause of the failure is analyzed.

Furthermore, in the above-mentioned computer system, it is also common practice for maintenance personnel of the device to analyze the failure location and replace parts. At this time, the information collected from the channel processor CHP for analyzing the cause of the failure is required to be detailed and accurate.

[Problem that the invention seeks to solve]

In the conventional method, when a fault in a common part can be identified in a certain channel, in order to prevent it from affecting the operation of other channels, it is necessary to take measures such as encoding the detailed information in the control information area of each channel. and retained it until it was output to the log.

Therefore, each channel requires a logout information storage area for each channel, and since the logout information is processed to save storage space, this logout information can be used to identify the failure detection location. I was unable to do so adequately.

Furthermore, among failures that occur in common parts, if the channel cannot be identified or failures that cannot guarantee normal operation thereafter, they are reported to the CPU as more serious failures, but even in such cases, detailed information that is available was insufficient.

[Means for solving problems]

In a channel processor that controls multiple channels in common, the present invention does not provide a logout information storage area for each channel, and if a failure occurs in a common section and the channel can be identified, the problem is reported from the time of occurrence. Until termination, the failure can be detected without affecting the operation of other channels.
This provides a means for having the CPU report and, moreover, allowing the service processor to collect more detailed information than before, independently of the report processing.

FIG. 1 is an explanatory diagram showing the basic configuration of the present invention. In the figure, 2 is the central processing unit CPU;
is the channel processor CHP, 4 is the channel CH,
6 is the service processor SVP, 8 is the individual section, 9
15 is a common part, 15 is a first fault processing section, 16 is a second fault processing section, and 17 is a set of fault position display latches.

The fault location display latch 17 is a means for primarily displaying the location of the fault, such as the error detection latch (EDL) of each register in the channel processor CHP, and is identified by the individual section 8 or the common section 9. and the information is made available for collection directly by the service processor SVP.

When a failure is detected in the individual unit 8 or the common unit 9, the first failure processing unit 15 receives a failure processing request from the individual unit 8 or a failure processing request from the common unit 9 for which the channel can be specified. only the channels that are affected are treated as failures,
Report to CPU as channel failure.

In addition, if faults of the same type or different types repeatedly occur in the same channel or other channels while fault processing is in progress in one channel, all operating channels will be processed as channel faults, or a second channel fault will be processed.
A request is made to the failure processing unit 16 to process it as channel damage representing a severe failure state and report it to the CPU. In this case, the service processor
It also reports to the SVP, scans out each failure location display latch 17, and collects information.

However, if no other failure occurs during the failure processing of one channel, the processing of other channels being executed is continued as is.

[Effect]

According to the present invention, since detailed failure information is directly collected from the EDL etc. by the service processor SVP, there is no need to provide a logout information storage area for each channel as in the conventional method, and there is no need to provide a storage area for logout information for each channel. It also does not require temporary storage.

Therefore, since the amount of information is not limited by the size of the logout information storage area or log buffer, it is possible to collect a sufficient amount of available detailed failure information.

〔Example〕

FIG. 5 shows the configuration of a system according to an embodiment of the present invention, and FIG. 6 shows its processing flow.

In Figure 5, 1 is the main storage unit MSU, 2 is the central processing unit CPU, and 3 is the channel processor.
CHP, 4 is channel CH, 5 is input/output device I/
O, 6 is the service processor SVP, 8 is the individual section,
9 is a common part, 10 is a status register, 11 is an operating system OS, 12 is an error detection latch EDL, 15 is a first fault processing section, 16 is a second fault processing section, 18 is a first fault processing request flag, 19
2 represents a second failure processing request flag, and 20 represents an execution latch.

A large number of error detection latches EDLs in the channel processor CHP are integrated by related individual sections 8 and common sections 9, and when a failure condition is displayed, it is recognized by the corresponding individual section 8 or common section 9. Ru. Each of these EDLs is also configured as each stage of a shift register, and the contents can be scanned out according to instructions from the service processor SVP.

Each individual unit 8 has a 1-bit first fault processing request flag 18, and indicates the occurrence of a fault to a subordinate.
Sets the flag on when recognized by the EDL. This flag can be included as part of the control information for each channel of the stack memory shown in FIG. 3, for example.

Regarding a failure occurring in the common unit 9, if the corresponding channel CH can be specified, the corresponding one of the first failure processing request flags 18 is set to ON.

However, if the channel cannot be identified or if normal operation cannot be guaranteed as a whole, the second failure processing request flag 19 is set on as a serious failure. In this case, it is also possible to set on the first fault handling request flags corresponding to the individual units of all channels operating at that time.

The execution latch 20 is set on while the first fault handler 15 is performing fault handling.

Next, the functions of the first fault processing section 15 and the second fault processing section 16 will be explained with reference to the processing flow shown in FIG.

The first failure processing unit 15 checks the first failure processing request flag 18, and executes a process if it is on, and executes a process if it is off.

If the first fault processing request flag is on, whether the execution latch 20 is set on or not;
That is, it is checked whether or not the first failure process is currently being executed, and if it is on, it is executed, and if it is off, it is executed.

Since run latch 20 is off, it is set on. Then run:

The first fault processing is executed, the requested channel is registered in the table as a faulty channel, a channel control check (CCC) is set in the status register 10, and the result is reported to the operating system OS of the CPU. Then run:

Reset run latch 20 off.

If the first failure processing request flag is off in
Check the second failure processing request flag 19. Execute the on case and return to the off case.

If the execution latch is on, that is, a fault occurs in the same channel or another channel while processing the fault in the faulty channel, and if the second fault handling request flag is on, that is, in the common part. When a fault that has occurred cannot be identified and the channel being executed cannot be guaranteed or normal operation cannot be guaranteed thereafter, it is treated as a severe fault, channel damage (CD) is set in the status register 10, and reported to the CPU OS.

When the operating system OS receives a channel control check (CCC) or channel damage (CD) report from the channel processor CHP, it executes the corresponding recovery processing, such as initializing the channel or reloading the control memory. do.

Especially when reporting channel damage (CD),
service processor at the same time as the CPU
This is also done for SVP. In response to this, the service processor SVP reads each error detection latch EDL of the channel processor CHP by scanout, independently from the reporting process to the CPU, collects it as detailed information for failure analysis, and processes it. After completion, error detection latch
Reset the EDL.

[Effects of the Invention] As described above, according to the present invention, the information necessary for reporting a channel fault from the channel processor to the CPU is the first bit of 1 bit per channel (individual part) under the channel processor. A small amount of information such as the fault processing request flag and the second fault processing request flag of 1 bit per channel processor is required, and moreover, the service processor can collect more detailed fault information than before. This simplifies the fault handling function of the channel processor and facilitates fault analysis processing.

[Brief explanation of the drawing]

Figure 1 is a diagram showing the basic configuration of the present invention, Figure 2 is a diagram showing the configuration of a general computer system targeted by the present invention, Figure 3 is a diagram showing the configuration of the control mechanism of a channel processor, and Figure 4 is a diagram of the conventional system. FIG. 5 is a block diagram of a channel failure processing mechanism in the system, FIG. 5 is a block diagram of a system according to an embodiment of the present invention, and FIG. 6 is a processing flow diagram of the system of the embodiment of FIG. In Figure 1, 2 is the central processing unit CPU;
is the channel processor CHP, 4 is the channel CH,
5 is an input/output device I/O, 6 is a service processor
SVP, 8 is an individual part, 9 is a common part, 15 is a first fault processing part, 16 is a second fault processing part, 17 is a fault location display latch, CCC is a channel control check that reports a minor channel fault, and CD is a Represents a channel damage signal that reports severe channel failure.

Claims (1)

[Scope of Claims] 1. Includes an individual unit that individually and cyclically controls a plurality of channels and a common unit that sequentially processes processing requests generated from each channel. as a channel failure
The channel processor that reports to the CPU processes failures that occur in individual parts and reports them as channel failures.For failures that occur in common parts, if the channel operating in the common part can be identified, it processes them individually. A first fault handling means that performs the same processing as a fault that occurs in the common section and reports it as a channel fault, and when the channel cannot be identified, reports the completion of all channels operating under the common section as a channel fault. a second fault handling means for detecting a fault in one channel or reporting it as a fault more severe than a channel fault; and a set of fault location display latches for providing detailed fault information, from the detection of a fault in one channel until the fault is reported. If the same type of failure or different type of failure occurs in the same channel or other channels during this period, the failure is reported by the second failure handling means. If no failure occurs, normal processing is continued without affecting the operation of other channels being executed, and the first failure handling means or the second failure handling means is used to remove the failure from the CPU. A channel failure handling method characterized in that the detailed failure information can be read from a failure location display latch to a service processor independently of reporting processing.