JPH0283746A - Test method for fault processing function - Google Patents

Abstract

PURPOSE:To shorten the developing period of a device and to increase the reliability of the device by converting the scan data obtained by a diagnosing instruction into an internal signal code to produce a pseudo fault and performing the simulation of the fault processing logic. CONSTITUTION:An instruction interpreter 2 is called out of a logical simulator 4 via an existing adaptor 32 and reads each instruction out of an inspection program 10. If a fault input diagnosing instruction is detected, the instruction and an operand are stored in an instruction decoding processing part 21. Then the part 21 extracts the scan address of a subject logic and sends it to the logical simulator 4. The simulator transfers the internal signal name to a fault input logic 41 and destroys the designated signal name. Then an instruction 13 to be tested of the program 10 is carried out by the simulator 4. At this time point a pseudo fault occurs and a fault processing function works to produce a machine check interruption. As a result, a logical defect can be early detected and the developing period of a device is shortened together with improvement of the device reliability.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a fault handling function testing method, and more particularly to a fault handling function testing method in device simulation.

[Conventional technology]

Traditionally, data processing systems have been equipped with hardware and software for various fault handling functions (reporting the occurrence of faults, collecting fault information, retrying, isolating faulty parts, etc.) in order to improve their reliability. ing. Regarding testing of data processing systems, it is necessary to test these fault handling functions, and for this purpose, simulated faults are generated. Furthermore, in order to shorten the product development period and to improve logic quality, it is becoming increasingly important to perform logic simulations.

Among these, it is considered effective to use a functional verification program as a method for systematically verifying the logic of the entire system. This is a function verification program that performs normal gate-level simulation only on the part that is truly tested, and the auxiliary part for testing is functional-level simulation that immediately generates only the results of instruction operations. This is what we do. Therefore, it is essential to test the failure handling function through simulation using a function verification program, but this is rarely done. The reason for this is, first, that a fault injection method has not been established. The problem is that the failure handling function is more diverse than the normal instruction processing function, and the amount of processing involved is enormous, requiring a large amount of simulation computer time. Currently, time constraints are relaxed due to pseudo-procedural methods.

Incidentally, related methods of this type include, for example, Japanese Patent Application Laid-Open No. 59-448971.

[Problem to be solved by the invention]

The above-mentioned conventional technology does not take into account the realization of the same means as the actual machine that performs the fault injection procedure using diagnostic commands, and it is not possible to verify the fault handling function at the device level at the simulation stage. Even if a logic defect is detected, it takes time to remanufacture the LSI, disrupting the product development schedule, and making it difficult to maintain product reliability. In addition, developing a functional verification program specifically for device simulation is difficult in terms of man-hours and schedule, so it is necessary to share the program with that for actual devices.

The purpose of the present invention is to solve such conventional problems, to make it possible to run a fault handling function verification program that is the same as that of the actual machine in a device simulation, to detect logic defects early, and to shorten the development period of the device. 2. Improve quality and reliability. The purpose of this invention is to provide a fault handling function test method that can improve performance.

[Means to solve the problem]

In order to achieve the above object, the fault handling function testing method of the present invention is a testing method for computer systems having various logical scales. The method is characterized in that it converts the scan data into a corresponding binary internal signal code, generates a pseudo fault using the converted internal signal code, and performs a logic simulation of the fault processing function.

[Effect]

In the actual machine, the fault handling function verification program uses a diagnostic command as a fault injection procedure to clearly indicate the scan A-I node of the target logic. With this scan address, it is unknown in which part of the logic simulator the fault will be injected. The logic simulator performs fault injection operations based on internal signal names.

It would be possible to embed the internal signal names in the verification program in advance, but this would not be usable on the actual machine, and the signal names would change due to logic changes, making it difficult to manage.

Therefore, it is necessary to replace the scan address of the target logic specified in the diagnostic command with an internal signal name before passing it to the logic simulator. In the present invention, within a device simulation system, a function and a conversion function for converting a scan address into a logical internal signal name code are provided in a functional module called a communication routine that controls the interface between an instruction interpreter and a logic simulator. Incorporating a table enables fault injection using diagnostic commands.

By converting the scan address specified by the diagnostic command into an internal signal name code within the communication routine, the verification program can perform a fault injection procedure for all fault injection sites existing in the computer system.

〔Example〕

An embodiment of the present invention will be described below in detail with reference to the drawings.

In this embodiment, a fault injection means using a diagnostic command is implemented so that the same fault handling function verification program as that of the actual machine can be run in the device simulation.

FIG. 1 is a configuration diagram of an apparatus simulation system showing an embodiment of the present invention.

In FIG. 1, 1 is a pseudo main memory that realizes the logic of main memory by rough 1 to software, 2 is an instruction interpreter, and 3
1 is an adapter, 4 is a logic simulator, 10 is a verification program for testing the fault handling function, 11 is an initial setting section, ] 2 is a fault injection section, 13 is a tested 1-instruction (group), 1
4 is a machine check interrupt processing section, 15 is a result judgment section, 2
1 is an instruction M reading processing unit that decodes the instruction and extracts the scan address of the diagnostic instruction; 31- is a fault injection adapter;
32 is an existing adapter, and 41 is a fault injection logic.

The verification program 10 includes an initial setting section 11. which defines necessary data for the purpose of the test. Fault injection unit 12 of diagnostic commands (group) that performs fault injection procedures. Instruction under test for detecting pseudo-faults 13. Machine check interrupt processing unit 14 that collects execution result data. It is composed of a result determination section 15 that determines whether the execution result is correct or incorrect.

The instruction interpreter 2 is a pseudo procedure that executes normal general instructions and diagnostic instructions at a functional level by writing and operating functional operations supported by a computer system in a program. The diagnostic instruction for fault injection is a privileged instruction, and the instruction is decoded by the instruction decoding processing unit 21 to extract the scan address.

The adapter 3 is an existing adapter 3 that connects the instruction interpreter 2 and the logic simulator 4 through normal instruction operations.
2, and a fault injection adapter 31 that passes fault injection data to the logic simulator 4. Further, the logic simulator 4 is configured with a program for the logical (game I level) functions of the computer system. The operation of this embodiment will be explained below.

It is assumed that the verification program 10 is stored in the pseudo main memory 1 in advance before execution. The instruction interpreter 2 is called from the logic simulator 4 via the existing adapter 32. Then, the instruction interpreter 2 reads each instruction from the verification program 10. If a diagnostic instruction for fault injection is detected among the read instructions, the instruction and operands are stored in the instruction decoding processing section 21.

This instruction decoding processing unit 21 extracts the scan address of the target logic. Thereafter, from the instruction interpreter 2 via the adapter 3 (the extracted scan address is converted into a corresponding internal signal name by the fault injection adapter 31 (see FIG. 2 below)), the gate-level logic simulator 4 to move to.

The logic simulator 4 assigns internal signal names to the fault injection logic 41.
give it to Fault injection logic 41 destroys the specified signal name. The above operations complete the fault injection.

First, when the instruction to be tested 13 of the verification program 10 is read by the instruction interpreter 2, it is directly executed by the logic simulator 4 via the adapter 3.

Here, the logic into which a fault has been injected in advance and the logic referenced by the instruction under test 13 are the same. Therefore, a pseudo failure occurs at this point. After a pseudo fault occurs, the fault processing function implemented within the logic simulator 4 is activated and a machine check interrupt is generated. When a machine check interrupt occurs, machine check interrupt storage information is stored in a fixed area. When the above operations are completed and the instruction execution operation returns, the process returns from the gate level of the logic simulator 4 to the instruction interpreter 2 at the machine language level via the adapter 3. And verification program 1
The machine check interrupt processing section 14 of 0 executes machine check interrupt processing, and if the result judgment section 15, which has the ability to judge pass/fail, determines that the product is defective, an error report is sent.

The instruction interpreter 2 sequentially performs the steps.

FIG. 2 is a diagram showing an outline of the processing of the failure injection adapter 31.

The scan address passed from instruction interpreter 2 is
It is stored in the scan address stacker 101. The conversion control unit 102 detects that the conversion table 1 is stored.
03, the internal signal corresponding to the corresponding scan address is extracted and stored in the signal name stacker 104. Thereafter, it is passed to the logic simulator 4 as an internal signal name code.

In this way, in this embodiment, it is possible to perform fault handling function verification in a device simulation environment using a function verification program.

Furthermore, even if the fault injection method or internal signal name changes when ported to another computer system, this embodiment can be applied to any computer system configuration as long as the contents of the conversion table are stored in each system. It is easily applicable regardless of the situation.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to run the same fault handling function verification program as in the actual machine in a device simulation, so logical defects can be detected early and the development period of the device can be shortened.2 Quality and reliability can be improved. You can improve your skills.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a device simulation system for explaining a fault handling function testing method showing an embodiment of the present invention, and FIG. 2 is a diagram showing a data flow of the fault injection adapter in FIG. 1. 1: Pseudo main memory, 2: Instruction interpreter, 3: Adapter, 4: Logic simulator, 10: Verification program, ]1
: Initial setting section, 12: Fault injection section, ], 3: Tested]・
Instructions (group), 14: Machine check interrupt processing unit, 15
:Result determination unit, 21. : D Engineering AG decoding and scan address extraction section, 31: Failure injection adapter, 32
: Existing adapter, 41: Fault injection logic, 101 Niscan address stacker, 102: Conversion control unit, ]03: Conversion table, 104: Signal name stacker. Patent applicant: Hitachi, Ltd. (two idiots) Agent: Patent attorney Masatoshi R. -, r;'J.

Claims (1)

[Claims] 1. In a testing method for computer systems having various logical scales, converting scan data given by a fault occurrence procedure using a diagnostic command into a binary internal signal code corresponding to the scan data using a conversion table, A fault handling function testing method characterized by generating a pseudo fault using the converted internal signal code and performing a logic simulation of the fault handling function.