JPS5833579B2 - information processing equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information processing device having a function of automatically detecting malfunction of the device and automatically recovering from the malfunction by re-executing a command or the like.

Before shipping an information processing device, it is necessary to test the normality of all its functions in advance, but it is difficult to test the malfunction detection function and especially the re-execution function.

That is, since the device is naturally designed so as not to malfunction under normal conditions, the malfunction detection mechanism does not normally operate, and the normality of the detection mechanism cannot normally be verified.

Furthermore, since the re-execution function assumes a serious malfunction, it becomes increasingly difficult to verify.

Conventionally, the following methods are known as methods for verifying the malfunction detection mechanism and re-execution function of a device.

One is to provide a function that forcibly inverts only the parity pit in maintenance mode.

If this function is used, the normality of the parity check circuit can be confirmed, but parity errors occur throughout the device, and it cannot be used to verify the re-execution function.

Next, the mask check latch, which is a set of check latches, is set to 1 asynchronously.

According to this method, it is not possible to verify the normality of the check latch, but since the device operates as if a malfunction had occurred, it can be used to tentatively verify the re-execution function.

However, the disadvantage of this method is that if a problem with the re-execution function is discovered, there is no way to reproduce it and the cause of the problem cannot be investigated, and the data of the calculation process is not incorrect. The problem is that it is not possible to verify the operation if there is an error in the data.

Another method is to compare the set value of the address switch on the panel with the microinstruction address in a microprogram-controlled processing device, and when a match is found, the mask check latch, general check latch, and even general data This involves verifying by making temporary wiring that forces the latch to be set.

This method is far superior to conventional techniques in that the time and place at which pseudo-malfunctions occur can be set quite freely.

However, the problem with this method is that the address switches on the panel and the location of the simulated failure must be manually set, which requires a lot of time and effort. .

Another method is to provide a register whose value can be set with a special command instead of the address switch on the panel in the above method.
Some devices compare this register with the microinstruction address.

According to this, the comparison address can be automatically set by a program, which greatly reduces time and effort.

However, even in this method, the location where a pseudo failure occurs is determined by temporary wiring set manually, and the location where the failure occurs is not automatically set.

SUMMARY OF THE INVENTION An object of the present invention is to provide a means for automatically setting a location where a pseudo failure occurs using a program without using temporary wiring.

Another object of the present invention is to provide a means for reducing the time and effort required to verify the normality of the failure detection mechanism and re-execution function.

Another object of the present invention is to provide a means that enables more complete verification by targeting many combinations of states in the verification of the failure detection mechanism and re-execution function.

Another object of the present invention is to provide a means for achieving the above purpose by rationalizing the use of various functions that the processing device has for other purposes, without providing many dedicated circuits.

As is well known, many information processing apparatuses are provided with a function for independently setting values to internal flip-flops and reading the values, in addition to a normal operation control circuit.

The setting of values for this flip-flop is called scan-in, and the reading of values is called scan-out.

For this scan-in and scan-out, scan address lines for specifying the address of the flip-flop are wired throughout the device, and the target flip-flop is recognized by decoding the address on the receiving side.

The present invention is designed to specify a location where a pseudo fault occurs using a scan address line, and to generate a pseudo fault by forced scan-in during normal operation.

The forced scan-in signal is generated from the output of the microinstruction address comparator and is sent out for as long as it takes for the pseudo-failure to occur.

Hereinafter, the contents of the present invention will be explained in detail with reference to the drawings.

FIGS. 1 and 2 show an embodiment of the present invention.

Here, the control memory 2 is a memory that stores a microprogram, and is accessed by the microinstruction address register 1, and read data is set in the microinstruction register 3.

Address comparison register 5 and scan address register 7
In both cases, set data from the program is input through line 4, which means that data can be set using a special command.

The scan-in/scan-out control section 10 outputs various signals, but here a scan-in signal 11 and one scan-in data are shown.

In the embodiment of the present invention, the output of the address comparison circuit 6 that compares the contents of the microinstruction address register 1 and the address comparison register 5 is ORed with the scan-in signal 11 and the scan-in data 12, respectively, and
It is distributed to each part of the apparatus through an interface 13 and a scan-in data interface 14.

The output of the scan address register 7 is also supplied to each part of the device through a data line 8, and on the receiving side, a scan address decoding circuit 9 recognizes the target flip-flop and generates a scan-in signal 15 for the corresponding flip-flop.

FIG. 2 shows an example of the configuration of the target flip-flop.

In FIG. 2, the target flip-flop (FF) normally operates with data 16 set through a timing signal line 17.

At the time of scan-in, the values specified by the scan-in data 14 and the scan-in signal 15 are set through the AND circuit 19 and the NOT circuit 20.

Next, the operation in the pseudo-failure occurrence mode will be explained.

Once the time and place of the pseudo-failure occurrence have been set, the program uses a special command, such as a diagnostic command ◆, to determine the point of failure occurrence (
A value expressed by a microinstruction address (step) is set in the address comparison register 5, and a value expressed by a scan address is set in the register 7.

After making the following preparations, we will begin running the test program.

When the pseudo-fault occurrence setting point is reached, a match between the microinstruction address register 1 and the address comparison register 5 is detected by the comparison circuit 6, and the output thereof is ORed with the scan-in signal 11 and the scan-in data 12 by the OR circuit 18, and the device outputs the signal. Distributed to each department.

On the other hand, the scan address register 1 is decoded by the decoding circuit 9, and the target flip-flop is designated.

The flip-flop designated by the scan address register 7 (see FIG. 2) is forcibly scanned in even though it is in normal operation, creating the same state as if there had been an apparent fault.

Thereafter, failure processing and re-execution are performed based on the functions of the device, so it can be verified by checking the normality of the operation.

As explained above, according to the present invention, in an information processing device that has a function of automatically detecting a malfunction in the device and automatically recovering it by re-executing a command, etc. Verification of executive function becomes possible more completely, in a shorter time, and without human intervention.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 shows an example of the configuration of a pseudo-failure flip-flop. 1...Microinstruction address register, 2...
... Control memory, 3... Micro instruction register, 4... Set data line from program, 5... Comparison address register, 6.
... Address comparison circuit, 7 ... Scan address register, 8 ... Scan address line, 9 ... Scan address decoding circuit, 10
...Scan-in, scan-out control section, 1
1...Z scan-in signal, 12...scan-in data, 13...scan-in interface, 14...scan-in data
Ink face, 15... concerned flip-flop scan-in signal, 16... normal operation data line, 17... timing signal line, 18...
...OR circuit, 19...AND circuit, 20...
...Knot circuit.

Claims (1)

[Claims] 1. In an information processing device that is equipped with a function to automatically detect a device malfunction and automatically recover by re-executing a command, etc., the flip-flops inside the device can be addressed completely independently of the state of the normal operation control circuit. A scan-in means for specifying and setting or resetting, an address comparison register whose value can be set by a special instruction, a means for comparing the address comparison register with an instruction address or a microinstruction address, and an output of the comparison means. means for ORing the scan-in means of the scan-in means and the scan-in signal respectively, and only when there is an output from the comparison means, the flip-flop with the specified address is operated by a normal operation control circuit. Set or reset completely independently of the state of the system, generate a pseudo device failure during general command processing to be executed later, and automatically perform a normality check of the device malfunction detection function and re-execution function. An information processing device characterized by: