JPH03191886A - Logic package inspection system - Google Patents

Abstract

PURPOSE:To improve an inspection efficiency by comparing an output pattern fed from patterns to be inspected in accordance with a pattern for inspection with an expected value and specifying a fault part when the result of a comparison shows a disagreement. CONSTITUTION:A logic simulation on a logic package 2 is executed by software simulation means 11 and, at the same time, the input pattern information of the simulation is taken out. Then, after an inspection request signal 100 is turned on, an inspection input pattern is transferred to a test pattern input unit 5 via an input pattern storing unit 8. After the completion of transfer, an inspection starting signal 101 is turned on, input values from the input unit 5 are selected by an input selector 6 and the inspection of the logic unit 14 of the package 2 is executed. When an inspection termination signal 102 is turned on the termination of the inspection, after an output pattern transfer signal 103 is turned on, an inspection output pattern is transferred from an output pattern storing unit 9 to a host computer 4. The computer 4 compares the inspection output pattern with the output pattern of the simulation by using comparison means 12.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a logic package inspection system, and more particularly to a system that inspects a logic package while it is installed in a device.

Prior Art Conventionally, the logic package inspection method was to create a new inspection cover pattern that operates a specific function of the logic package, input the inspection output pattern, and output the results as a terminal or list. There is a method that involves manual analysis. If the analysis results show that the logic package is malfunctioning, manually narrow down the locations that are causing the malfunction using circuit diagrams or logical formulas, and then use a well-known oscilloscope or logic analyzer to target those locations. , more detailed waveform patterns were obtained and the cause of the malfunction was identified.

In the conventional inspection method, when providing a human cover pattern for inspection to a logic package, the designer has to program a new input pattern even though there is a human cover pattern used in software simulation during device design. was there.

Another drawback is that it is necessary to manually determine whether the test output pattern is normal or incorrect and to narrow down the locations of incorrect operations.

Furthermore, it takes a lot of effort to attach and detach the oscilloscope and logic analyzer when squeezing dust occurs, resulting in poor inspection efficiency.

OBJECTS OF THE INVENTION The present invention has been made to solve the above-mentioned conventional drawbacks, and its purpose is to provide a logic package inspection system with high inspection efficiency.

Structure of the Invention The logic package inspection system according to the present invention includes a pattern input means for inputting a test pattern to a package under test, and an output pattern and an expected value pattern sent from the package under test according to the test pattern. and a comparison means for comparing the two, and when the comparison result of the comparison means indicates a mismatch, the output pattern is used to identify a failure location.

Example Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of a logic package inspection system according to the present invention.

In the figure, a device 1 to be inspected includes a plurality of logical packages. Each logic package 2 to be inspected here has a test pattern input section 5, an input selector 6, and a test pattern output section 7 as additional circuits for inspection in addition to its original functions. Further, it is assumed that each logic package is configured so that an adapter 15 can be attached thereto. Note that 16 is a normal input section for inputting signals during normal operation.

The test pattern input unit 5 is the part that first receives the input test pattern in the logic package.

The input selector 6 is a part that selects either the normal signal or the test pattern as input to the logic section which performs its original function.

The test pattern output unit 7 is a part that outputs the pattern of values of registers and memories (not shown) to the outside of the logic package after operating the logic unit using the test pattern.

The adapter 15 is provided for the purpose of detecting the human output value of the gate of the logic package 2, and is not built into the logic package, but is attached when inspecting the logic package. That is, in order to move from testing one logic package to the next logic package, the interface control unit 10 is connected to the logic package to be tested, and the adapter 15 is reattached to the logic package to be tested.

Further, an interface 3 is provided for connection between the logical package 2 and the host computer 4. The interface 3 includes an input pattern storage section 8, an output pattern storage section 9, and an interface control section 10.

The human cover turn storage section 8 serves as a buffer for providing the input cover turns used in software simulation to the logic package at the time of design.

The output pattern storage section 9 compares the patterns of the register and memory values output from the test pattern output section 7 with means 12.
This is the part that serves as a buffer for feeding.

The interface control unit 10 has a function of transmitting a pattern to the human cover turn storage unit 8 and turning on an inspection start signal 101 when an inspection request signal 100 is input from the host computer 4, and outputting an inspection end signal 1 from the logic package.
02 is input, the output pattern storage section 9 receives the pattern, and when the reception is completed, the output pattern transfer signal 1Gi9 is turned on to control the output pattern storage section 9 to send the pattern. . This interface control unit 10 is commonly used for all logic packages to be inspected. Furthermore, software on the host computer 4 includes a software simulation means 11, a comparison means 12, and a failure location/
A bug location specifying means 13 is provided.6 Next, the inspection procedure by this system will be explained using FIG.

FIG. 2 is a conceptual diagram showing the inspection procedure by this system.

First, a logic simulation for the logic package 2 is performed by the software simulation means 11 (step 2o), and at the same time, the human cover turn information of the simulation is extracted (step 21). Next, after turning on the inspection request signal 100, the inspection type cover turn is transferred to the test pattern input section 5 via the input cover turn storage section 8. After the transfer is completed, the inspection start signal 101
is turned on, the input selector 6 selects the input value from the test pattern input section 5, and the logic section 14 of the logic package 2 is tested (step 22).

Register and memory values under inspection are checked one by one every clock.
The test pattern output unit 7 transfers the data to the output pattern storage unit 9. Further, the values of the gates under test are also transferred one by one to the output pattern storage unit 9 via the adapter 15 every clock (step 23).

When the test end signal 102 is turned on with the end of the test, the output pattern transfer signal 103 is turned on, and then the test output butter is transferred from the output pattern storage section 9 to the host computer 4. The host computer 4 uses the comparison means 12 to compare the transferred inspection cover pattern with the simulation output pattern (step 24) that is the expected value (step 25). Then, when the comparison result shows a mismatch, the failure location/bug location is identified using the failure location/bug location identifying means 13 (step 26).

Note that a program for comparing inspection results with expected values and a program for identifying failure locations and bug locations can be easily realized by those skilled in the art.

In other words, in the inspection system of the present invention, the simulation pattern used at the time of design is used as the inspection cover pattern, and the host computer automatically checks the comparison between the simulation result pattern and the inspection cover pattern.
Based on the results, failure locations and bug locations are identified.

As described in detail, according to the present invention, there is no need to create a new inspection type cover turn at the time of inspection, and it is possible to determine whether the cover turn for detection is normal or incorrect, and further narrow down the incorrect location in the case of incorrect detection. There is no need to manually analyze the data, and this has the effect of preventing omissions during inspection. Another advantage is that the oscilloscope and logic analyzer need only be attached and detached once to check for irregularities, thereby shortening the inspection period.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a logic package inspection system according to an embodiment of the present invention, and FIG. 2 is a schematic diagram of the inspection procedure by the inspection system of FIG. 1. Explanation of symbols of main parts 11...Software simulation means 1
2...Comparison means 13...Failure location/bug location identification means Fig. 2

Claims (1)

[Claims] (1) Comprising a pattern input means for inputting a test pattern into a package under test, and a comparison means for comparing an output pattern sent from the package under test according to the test pattern with an expected value pattern. The logic package inspection system is characterized in that when the comparison result of the comparison means indicates a mismatch, the output pattern is used to identify a failure location.