JPH0713655B2 - Integrated circuit test method - Google Patents

Description

The present invention relates to a method for testing an integrated circuit, and more particularly to a method for testing an integrated circuit in which a logic circuit and a memory circuit coexist (hereinafter referred to as "logic mixed memory integrated circuit"). It is about.

[Conventional technology]

Conventionally, as a test of this kind of logic mixed memory integrated circuit, a test pattern created by simulating the entire circuit including a memory section has been used.
Further, in the case of a circuit that can test the memory unit independently of the logic unit, only the memory unit was tested using a memory dedicated tester.

[Problems to be Solved by the Invention]

In the conventional test method described above, when a test pattern created by simulating the entire circuit is used, when an error occurs in the tester due to a failure, it is determined whether the failure is in the memory section or the logic section. Since this is not possible, there is a drawback that failure analysis becomes very difficult.

Also, when testing the memory section with a memory dedicated tester,
If an error is detected in the entire circuit and the memory section is normal, it can be indirectly diagnosed as a failure of the logic section unrelated to the memory, but the failure of the logic section around the memory such as the memory control circuit In some cases, there was a problem that the memory part could not be separated from the failure.

Further, in the case of a reconfigurable memory circuit having redundant bits, even if there is a failure in the memory section, it can be reconfigured and used as a normal memory, but at this time, the logic section other than the memory is normal. Since it cannot be confirmed whether or not the memory is reconfigured until the memory is reconfigured and retested, the reconfiguration is wasteful and extra cost and man-hours are required.

[Means for Solving the Problems]

In order to solve such a problem, the present invention provides a method for testing an integrated circuit in which a logic circuit and a memory circuit are mixed,
The output of the memory is always set to an indefinite value and the logic part is tested using a test pattern created by simulation.Only the memory part is tested using the memory test pattern generated by the memory part test pattern generation part. The test of the entire integrated circuit is performed using a test pattern created by simulating the output according to the memory operation.

[Action]

In the integrated circuit testing method according to the present invention, the logic section can be tested and diagnosed regardless of whether the memory section has a failure, and the memory section can be tested independently of the logic section. Can be tested.

〔Example〕

FIG. 1 is a flow chart for explaining an embodiment of an integrated circuit testing method according to the present invention. This embodiment comprises first to third test steps. In the first test process, the circuit data and the input pattern of the simulation are input (steps 1 and 2), the simulation is performed with the memory output always being an indefinite value (step 3), and the created logic part test pattern (step 4) is used to test the logic part. Next, in the second test step, only the memory section is tested using the memory section test pattern such as the march pattern or gallop pattern uttered by the memory section test pattern generating section based on the input circuit data (step 1). (Step 5). Next, in the third test process, the circuit data and the input pattern of the simulation are input (steps 1 and 2), the entire circuit including the memory operation is simulated (step 6), and the test of the entire circuit created The entire integrated circuit is tested using the pattern (step 7).

FIG. 2 is a block diagram showing an example of a logic mixed memory integrated circuit to which the integrated circuit test method according to the present invention is applied. In the figure, a logic mixed memory integrated circuit 10 includes a RAM 13 surrounded by registers 11 and 12 having a scan function.
And a logic unit 14.

In the first test step, the output of RAM13 is always set to an indefinite value and the test is performed using a test pattern created. Therefore, the expected value of register 12 becomes indefinite at the timing of reading the data read from RAM13, and At the timing when the data is masked and the register 12 fetches data other than the RAM13, the expected value becomes final
The logic part 14 other than M13 can be tested. As a result, if the logic unit 14 is normal even if the RAM 13 fails, the test result is OK (good), and conversely, if the test result is an error, it can be considered that the logic unit 14 has a failure.

In the second test step, the test is performed using the test pattern for the memory test, but since the RAM 13 is surrounded by the logic section 14, the RAM 13 is read and written through the registers 11 and 12 and a part of the circuit of the logic section 14. Will be tested. At this time, since the registers 11 and 12 and the logic circuit 14 have been tested in the first test process, when an error occurs in the second test process, it can be regarded as a failure of the RAM 13.

In the third test step, since the test is performed using the test pattern created by simulating the entire circuit including the memory operation, it is possible to test whether the entire integrated circuit operates normally. Further, it is possible to diagnose whether or not there is a failure in the circuit at the joint between the RAM 13 and the logic unit 14.

〔The invention's effect〕

As described above, according to the present invention, the logic part can be tested and diagnosed regardless of the presence or absence of a failure in the RAM part by performing a test using a test pattern created by a simulation in which the output of the memory part is an indefinite value. It is possible to test the memory part independently of the logic part by testing with the test pattern for the memory part, and by testing with the test pattern created by simulation of the entire circuit including the memory operation, the entire circuit can be tested. Since the test can be performed, it is possible to perform a sufficient test for failure analysis, and it is possible to easily isolate a failure point when an error occurs in the tester.

In particular, in the case of a reconfigurable memory circuit having redundant bits, even if there is a failure in the memory part, it is possible to test whether the logic part is normal. Even if the chips that cannot be used are checked in advance, there is an effect that extra cost and man-hours can be significantly reduced because wasteful reconfiguration is performed.

[Brief description of drawings]

FIG. 1 is a flow chart for explaining an embodiment of an integrated circuit testing method according to the present invention, and FIG. 2 is a block diagram showing a logic mixed memory integrated circuit. 10 …… Logic mixed memory integrated circuit, 11, 12 …… Register, 1
3 …… RAM, 14 …… Logic section.

Claims (1)

[Claims] 1. A method for testing an integrated circuit in which a logic circuit and a memory circuit coexist, in which a logic part is tested by using a test pattern created by performing a simulation with an output of the memory as an indefinite value. A second step of testing only the memory section by using the memory section test pattern generated by the memory section test pattern generation section, and integration using a test pattern created by simulating the output of the memory according to the memory operation And a third step of testing the entire circuit.