JP2595263B2 - Automatic test pattern creation method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a method for automatically generating a test pattern of a test program for a high-performance device such as a microprocessor and a peripheral LSI. The device under test is operated on the device, and the signal level of each pin is normally set to High level, Low level through a comparator.
A temporary storage means for converting the pin information into a ternary state of a level and an intermediate level and temporarily storing the pin information in a test memory; and a drive pattern for applying all pins other than the intermediate level pins to the device under test according to the pin information. Conversion means for converting the data into at least one
Switching means for disconnecting an input driver and reconnecting an output comparator for each pin; comparing means for comparing pin information obtained from the output comparator with an expected value at that time; A connection means for judging whether or not to be connected as it is or to be connected to an input driver for switching, and the switching means, the comparison means, and the judgment connection means until each pin of the device under test is assigned to a correct input / output state. It is configured to include a repetition means for repeating, and a test pattern storage means for storing a desired test pattern including the input / output pin identification information obtained by the repetition means in the test memory.

[Industrial applications]

The present invention relates to a test pattern automatic generation method for a test program for a high-performance device such as a microprocessor and a peripheral LSI.

In an integrated circuit (IC) IC tester, an input pattern to be input to a device and an expected output pattern to be output from the device are usually stored in a test memory, and an input signal is input to the device via a driver according to the input pattern. Is applied, a comparator determines whether an output pattern that matches the expected output pattern has been output from the device, and determines whether the device is non-defective or defective.

However, with the sophistication of the functions of the microprocessor and peripheral LSIs, the input pattern and the expected output pattern in the test using the LSI tester become complicated, and the limit of manual pattern creation is becoming limited. Therefore, it has become common to create test patterns by collecting pin information from non-defective devices.

[Conventional technology]

In order to test whether an integrated circuit (IC) composed of a logic circuit operates properly, a tester as shown in FIG. 5 is generally used. Reference numeral 50 denotes a device to be inspected (Device Under Test (DUT)); 51, a test memory for storing an input pattern to be input to the device 50 and an expected output pattern to be output from the device 50; A pin electronics circuit that drives an input signal of an appropriate level to a pin through a driver and compares the output signal with an expected level of an output pin. 53 is a control program storage memory that stores a test program. Is a control unit that controls the test memory 51 and the pin electronics circuit 52 according to a control program.

During a normal test, an input pattern from the test memory 51 is applied to the device 50 via a driver in the pin electronics circuit 52, and an output pattern output from the device 50 and an expected pattern output from the test memory 51 are compared with the pin electronics circuit 52. The device 50 determines whether the non-defective product is a defective product or not by comparing them with each other.

When a device is tested using such a tester, there are a functional test and an electrical characteristic test as test methods. The functional test is a test for checking whether a combinational circuit or a sequential circuit in a device operates theoretically correctly, and an extremely large number of input patterns are applied in order to inspect most of the inside. In functional tests,
A logical comparator based on exclusive OR is used to compare the output pattern with the expected output pattern. On the other hand, the electrical characteristics test is a DC
AC for testing and testing characteristics such as delay time and setup time
There is a test in which the characteristics are examined by changing the level of the input voltage or changing the level of the reference voltage to be compared with the output voltage. In the electrical characteristic test, the output pattern and the expected output pattern are compared with an analog voltage value, so that an analog comparator is used.

However, with the sophistication of the functions of the microprocessor and peripheral LSIs, the input pattern and the expected output pattern in the test using the LSI tester become complicated, and the limit of manual pattern creation is becoming limited. Therefore, it has become common to create test patterns by collecting pin information from non-defective devices.

However, in the electrical characteristic test, the test pattern includes information for distinguishing an input pin, an output pin, and a bidirectional pin of the device 50 (hereinafter, referred to as pin identification information), and further, a high (H) state of the output voltage value. And low (L) state, it must contain expected information to check the level value. Conventionally, as an easy way to create a test pattern, pin identification information and an input pattern to the tester are manually created, and the expected output pattern is We have taken the method of sucking it from a good device.

[Problems to be solved by the invention]

As described above, in the conventional method in which only the expected output value is sucked from the non-defective device, the pin identification information and the input pattern are manually created while being considered by a human.
For a device such as a microprocessor having a very large number of pins and complicated functions due to prefetching of instructions (prefetching) and the incorporation of a cache, there has been a problem that it is not easy to create them.

It is an object of the present invention to provide a test pattern automatic creation method for automatically creating a test pattern including pin identification information from device pin information.

[Means for solving the problem]

The present invention is based on the fact that a non-defective device composed of an LSI such as a microprocessor is actually operated on an apparatus and a test pattern is collected. Since the information collected here has no distinction between input and output, it is converted into a test pattern including pin identification information required when driving a device under test having the same structure on the tester. In the present invention, the change to the test pattern follows the algorithm of the automatic pattern correction program, and the operation flow is shown in FIG.

In this operation flow, when connecting a driver, write "0" or "1" according to its logic, and when connecting a comparator, set "H" according to the expected high level, low level, and high impedance (intermediate level). ",
Write “L” and “Z”.

In step 10, all outputs of the channels corresponding to the pins are set to the comparator mode, and in step 11, the non-defective device under test is actually operated on the actual apparatus. Then, the temporary storage means converts the information into a ternary state of H, L, and Z via a comparator in the signal level LSI tester of each pin and temporarily stores the generated pin information in the test memory. That is, the pattern is sucked. In step 13, the conversion means converts all the channels of the LSI tester into the input driver mode, and further converts the ternary pin information in the test memory into a drive pattern. Here, the drive pattern is a pattern formed by converting L to 0 and H to 1. At the time of step 13, Z is not changed. The conversion means includes processing of a Z pattern, and in the next step 14,
The processing of the Z pattern is performed. That is, the corresponding pin is forcibly driven using the drive pattern, and the output level of the pin corresponding to Z is checked in step 140. Even if the output level is applied to the drive pattern,
The level becomes an intermediate level corresponding to Z, but there is a possibility that the level may have been changed to Z due to a temporary bus fight, so that a FAIL may occur. Therefore, in step 140, if Z is similarly output for the application of the drive pattern, PASS
Then, the process proceeds to step 142. In step 142, it is checked whether or not the intermediate level of the pin corresponding to Z is caused by strobe at the transition time from H to L or from L to H. For this purpose, the signal level is checked by moving the strobe time back and forth. Then, the process proceeds to step 143. If the state changes from Z to H or from Z to L due to the movement of the strobe, the process proceeds to step 144 to change Z to X. Where X
Is a signal indicating that it is time for a signal transition. If X, the comparator is turned off, the X pin is masked and removed from the inspection target, and the routine proceeds to step 15. Also, in step 143, if Z remains Z due to the movement of the strobe, the pin is set to Z (high impedance).
It is determined to be a pin, and the process proceeds to step 15 while keeping Z. If it is determined in step 140 that the drive pattern is to be failed by applying the drive pattern, Z is changed to an input pattern of 1 or 0, and the process proceeds to step 15. Therefore, in the conversion means before step 15, the X pin and the Z
A drive pattern of “1” and “0” with all pins except pins as input pins is obtained.

Next, using the drive pattern obtained by the conversion means, the switching means disconnects the input driver on the tester at least for each pin and reconnects the output comparator. In this operation flow, it is assumed that the driver is changed to the comparator one channel at a time.
At 15 this switching is performed. After switching, step 17
And 170, by comparing the pin information of H or L obtained from the output comparator with the expected value,
If they match, it indicates that it is an output signal from the device, and the output mode is maintained. If they do not match, in step 170, the output comparator is returned to the driver, and the mode is set to the input mode. And step
In step 18, the END is determined. If not END, the process returns to step 15 through step 19 by the repetition means, and the switching operation (step 15) and the comparison operation are performed until each pin of the device is assigned to a correct input / output state. (Step 16) and the judgment connection operation (Steps 17 and 170) are repeated. When the examination of all the channels and all the addresses in the test memory is completed by the above-mentioned repetition, Steps 18 to 200 are executed.
Here, the test pattern including the input / output pin identification information is filed by the test pattern storage means, and the processing is terminated.

[Action]

In the present invention, a signal from a non-defective device actually operating on the apparatus is taken up, the output mode is set one pin at a time by using a pattern of three values of H, L, and Z, and the pattern is otherwise set to the output mode. A test pattern including pin identification information is automatically created by giving the device a drive pattern for input again to the device and checking on a tester whether the output mode is correct.

〔Example〕

The operation flow of the present invention shown in FIG. 1 will be described in more detail with reference to FIG.

In this operation flow, when connecting a driver, write "0" or "1" according to its logic, and when connecting a comparator, set "H" according to the expected high level, low level, and high impedance (intermediate level). ",
Write “L” and “Z”.

(I) In steps 10, 11 and 12, the driver 322 in the pin electronics circuit 32 is first disconnected by turning off the relay circuit 321 and comparators 327 and 328 are connected to all pins of the device 30 via the buffer 326 to operate. The device 30 downloads the pattern. Each pin information of this pattern is represented by H, L, and Z as shown in FIG.
Value.

(Ii) Next, in step 13, the ternary pin information in the test memory is unconditionally changed to a drive pattern. Here, the drive pattern is defined as H / L as shown in FIG.
Is converted to 1/0.

(Iii) Next, in step 14, processing of the Z pattern is performed. twenty one
The device 30 is driven using the drive pattern described above.
At this time, Z is left as it is. Therefore, since the expected output value is only Z, this drive pattern
Should pass. However, a temporary bus fight may have occurred. Therefore, if Z changes to 0 or 1, the input mode is set by the conversion of H / L → 1/0. Also, if you pass, you move the strobe. If Z is H
Or, if it becomes L, the corresponding pin information becomes information at the time of input / output transition. In this case, the Z pattern at the time of input / output transition is OF
Set to F mode and mask the comparator. Or,
It may be adjusted to the state (0/1) before and after the pattern of Z.

(Iv) Next, the drive patterns obtained so far in steps 15, 16, and 17 are returned to the comparator one bit at a time as shown in FIG. At 22 in FIG. 2, the first channel is returned from 0 to L. In this case, only the first channel is in the output mode. If the drive pattern is PASSed, the first channel indicates that the device is receiving the output signal that is being output, and thus can be regarded as the output mode. FAIL is what you should drive,
Just return to the original 0/1.

(V) If the above procedure is repeatedly executed within the specified address range of the specified channel, a desired test pattern as shown in 23 of FIG. 2 can be obtained. This test pattern is clearly a test pattern including input / output pin identification information, and is used when an electrical characteristic test is performed on a tester for another device under test having the same structure as the device 30.

FIG. 3 is a block diagram of the present invention, showing a test pattern siphoning and automatic conversion device.

Reference numeral 30 denotes a microcomputer of a non-defective device under test (DUT), which is installed on a substrate 302 in an actual computer and is actually operating. In other words, if the device is a CPU, it fetches instructions from main memory in the computer, decodes the instructions, and executes arithmetic operations with the internal ALU for arithmetic instructions. In the case of a main memory reference instruction, an address is given to the main memory to read or write data in the main memory. Therefore, an input signal is applied to an input pin of the device 30, and an output signal is output from an output pin. 3 is an LSI tester. Reference numeral 31 denotes a test memory which stores an input pattern to be input to the device under test and an expected output pattern which will be output from the device under test. In the present invention, a drive pattern generated in the process of automatically creating a test pattern is used. It is also used as a temporary storage memory. 32 is a pin electronics circuit that drives an input signal of an appropriate level to the input pin of the device under test via a driver, and compares the output signal with the expected value of the output pin, and 33 is the test circuit of the present invention. A control program storage memory for storing a pattern automatic creation program and a test program at the time of inspection is a control unit for controlling the test memory 31 and the pin electronics circuit 32 according to the test pattern automatic creation program and test program of the present invention. is there.

In the present invention, the non-defective device under test 30 is actually operated on the actual apparatus, and the signal level of each pin is set to H, via the comparator in the pin electronics circuit 32 via the signal line 301 connected to each pin. The pin information converted into the ternary state of L and Z and generated is stored in the temporary test memory 31. That is, the pin information of all pins is collected first.

FIG. 4 is a configuration diagram of the pin electronics circuit 32 in the LSI tester 3 used in the present invention.

The input / output terminals of the pin electronics circuit 32 are called channels, and each pin of the device under test 30 is connected to a corresponding channel by a signal line 301. Therefore, it is possible to download the pin information of the device under test 30 via the channel, and to provide the pin information to the test device via the channel.

322 is an input driver, and the tester drive circuit is H
Each voltage value on the igh (H) side and the Low (L) side can be controlled by a program, and the input voltage can be changed. 321 is a relay circuit. Only when the corresponding channel is driven by the driver 322, the relay circuit 321
Turns on. A buffer 326 receives an input signal input from the outside via a channel. Each channel is directly connected to the input of the corresponding buffer 326, but is connected to the driver 322 via a relay circuit 321. Therefore, each channel supplies a signal to the outside only when the relay circuit 321 is ON. The input pattern in the test memory 31 is set as a drive pattern in the drive pattern register 324, and the waveform corresponding to the logic content in the drive pattern register 324 is synchronized with the clock timing selected by the clock selection circuit 325. 323 is formed. The formed waveform is Driver 3
22 and output from the driver 322 at an appropriate voltage value.

On the other hand, a signal input from the outside is supplied to a high-side comparator 327 and a low-side comparator 328 via a buffer 326.
And compared with the reference voltage VOH and the reference voltage VOL, respectively. The comparators 327 and 328 are both analog comparators. The output of each of the comparators 327 and 328 becomes a logical signal corresponding to coincidence or non-coincidence, and is supplied to the pattern comparator 329. Further, the expected output pattern output from the test memory 31 is set in the comparison pattern register 3210, and the content thereof is given to the pattern comparison circuit 329. The pattern comparison circuit 329 is a digital comparator formed by an exclusive OR operation, and outputs a FAIL signal if they do not match. When the comparator enable signal is disabled, the comparison by the digital comparator is not performed.

In the test pattern siphoning and automatic conversion apparatus described above, the program according to the test pattern automatic generation method of the present invention is stored in the control program storage memory 33, and is stored in the control unit 34 via the control unit 34 in accordance with the operation flow shown in FIG. Electronics circuit 32 and test memory
Control 31.

Next, how to use the test pattern automatically created by the present invention will be described.

The test pattern created by this algorithm is a copy of the operation of the actual device and is not basically intended for a function test.

The purpose is to investigate DC characteristics such as ViL, ViH, VOL, and VOH among the electrical characteristics of the device, and to investigate AC characteristics such as delay and setup.

As an example, a method of measuring the ViL and ViH characteristics will be briefly described.

A test is performed with an LSI tester using the test pattern obtained by this method, and the drive circuit of the tester can program-control the high-side and low-side voltage values.

As the input voltage is changed in the obtained pattern, a boundary value between the voltage value that matches the comparator pattern (expected value) and the voltage value that does not match is obtained. This is ViH
Or ViL.

Similarly, if the boundary value of the reference voltage of the comparator is obtained, it becomes VOH and VOL.

〔The invention's effect〕

As described above, according to the present invention, since the pin identification information is automatically obtained from the pattern obtained from the signal pickup of the device that is actually operating, a highly functional LSI device that performs any complicated operation , A test pattern can be automatically created easily.

[Brief description of the drawings]

FIG. 1 is an automatic pattern correction program flow, FIG. 2 is a schematic diagram of a conversion process of siphoning data, FIG. 3 is a block diagram of a siphoning and automatic converting device of a test pattern, and FIG. 4 is an LSI used in the present invention. FIG. 5 is a configuration diagram of a pin electronics circuit in the tester, and FIG. 5 is a configuration diagram of a commonly used tester. H, L, Z ... Pin information, 3 ... LSI tester, 10 ... Driver OFF comparator for all channels ON, 11 ... DUT RUN, 12 ... Download pattern, 13 ... Driver for all channels ON Yes, 14,140… PASS ?, 14,141 …… Change from Z to 0 or 1, 14,142… Check the signal level by moving the strobe back and forth, 14,143… The state has changed? , 14, 144… Changed from Z to X, 15… Changed the driver to a comparator for each channel, 16… DUT RUN, 17… PASS ?, 18… END ?, 19… NEXT bit, 170… Return to driver, 200: File, 201: End, 30: Device under test, 31: Test memory, 32: Pin electronics circuit, 33: Control program storage memory, 34: Control unit, 302 …… Substrate, 327,328 …… Comparator.

Claims (1)

(57) [Claims] (1) A signal from a real device is sucked up.
In a test program creation method for an integrated circuit for creating test pattern data, a device under test is operated on an apparatus, and a signal level of each pin is measured by an analog comparator (hereinafter referred to as a comparator).
And a temporary storage means (10, 11, 12) for converting the pin information into a ternary state of a high level, a low level, and an intermediate level, and temporarily storing the pin information in a test memory. A conversion means (13) for converting the pin information into a drive pattern to be applied to the device under test by allocating a logical value "1" of the input driver and allocating a logical value "0" of the input driver to the low-level pin. , 14), switching means (15) for disconnecting the input driver and reconnecting the output comparator for at least one pin of the device under test to which the drive pattern is applied, and expecting pin information obtained from the output comparator at that time. Whether the output comparator should be directly connected or switched to an input driver depending on whether the comparison means (16) compares the value with the comparison means (16) Determining connection means for switching is determined whether to connect (1
7, 170), the pin determined to be coincident by the comparing means (16) is regarded as an output pin, the pin determined to be mismatched by the comparing means (16) is regarded as an input pin, and each pin of the device under test is The switching means (15), the comparison means (16), and the judgment connection means (1
Repetition means (19) for repeating each operation by (7, 170)
And a test pattern storage means (200) for storing a desired test pattern including the input / output pin identification information obtained by the repetition means (19) in the test memory. .