JPS5549761A - Logical operation circuit testing unit - Google Patents

Logical operation circuit testing unit

Info

Publication number
JPS5549761A
JPS5549761A JP12224578A JP12224578A JPS5549761A JP S5549761 A JPS5549761 A JP S5549761A JP 12224578 A JP12224578 A JP 12224578A JP 12224578 A JP12224578 A JP 12224578A JP S5549761 A JPS5549761 A JP S5549761A
Authority
JP
Japan
Prior art keywords
operation circuit
logical operation
circuit
tri
output pin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12224578A
Other languages
Japanese (ja)
Inventor
Nobuo Wakatsuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP12224578A priority Critical patent/JPS5549761A/en
Publication of JPS5549761A publication Critical patent/JPS5549761A/en
Pending legal-status Critical Current

Links

Landscapes

  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

PURPOSE: To facilitate a test for a large-scale logical operation circuit by providing a means which applies test data to the output pin in a high-impedance state of a tri- state element in the ligical operation circuit.
CONSTITUTION: Logical operation circuit 1 consists of IC 3 mounted on IC board 2, tri-state element 4 which can take a high-impedance state besides binary states, external input terminal 5, external output terminal 6, output pin 7 in the high-impedance state of tri-state element 4, observation point 8 and clock terminal 9. The test pattern stored in testpattern storage circuit 19 is applied to output pin 7, and the operation result of logical operation circuit 1 for the test pattern above is read from external output terminal 6 or observation point 8 and is sent to output comparator circuit 17 through I/0 control circuit 14 and is compared with a correct solution value.
COPYRIGHT: (C)1980,JPO&Japio
JP12224578A 1978-10-03 1978-10-03 Logical operation circuit testing unit Pending JPS5549761A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12224578A JPS5549761A (en) 1978-10-03 1978-10-03 Logical operation circuit testing unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12224578A JPS5549761A (en) 1978-10-03 1978-10-03 Logical operation circuit testing unit

Publications (1)

Publication Number Publication Date
JPS5549761A true JPS5549761A (en) 1980-04-10

Family

ID=14831177

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12224578A Pending JPS5549761A (en) 1978-10-03 1978-10-03 Logical operation circuit testing unit

Country Status (1)

Country Link
JP (1) JPS5549761A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6028208A (en) * 1983-07-27 1985-02-13 松下電器産業株式会社 Method of assembling resistor
JPS6478331A (en) * 1987-09-19 1989-03-23 Fujitsu Ltd Automatic production system for test pattern

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6028208A (en) * 1983-07-27 1985-02-13 松下電器産業株式会社 Method of assembling resistor
JPH0546081B2 (en) * 1983-07-27 1993-07-13 Matsushita Electric Ind Co Ltd
JPS6478331A (en) * 1987-09-19 1989-03-23 Fujitsu Ltd Automatic production system for test pattern

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