JPS5479569A - Intergrated circuit - Google Patents
Intergrated circuitInfo
- Publication number
- JPS5479569A JPS5479569A JP14753777A JP14753777A JPS5479569A JP S5479569 A JPS5479569 A JP S5479569A JP 14753777 A JP14753777 A JP 14753777A JP 14753777 A JP14753777 A JP 14753777A JP S5479569 A JPS5479569 A JP S5479569A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- test
- signal
- terminal
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Tests Of Electronic Circuits (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Abstract
PURPOSE: To make it possible to make unit tests after mounting by equipping an IC with a logic circuit and memory circuit which process and memorize test patterns, memory circuit stored with rigth-answer values which correspond to test, patterns and comparator circuit which compares them.
CONSTITUTION: The IC is composed of control circuit 103, read-only memory circuits 104 and 106, selector circuit 105, logic circuit 107, comparator circuit 108, etc., and input terminals 101 and 102 are supplid with a test mode operation command and non-test mode operation respectively. As a result, circuit 103 commands circuit 105 to send a signal from terminal 102 to circuit 107, which sends a signal selected by circuit 105 to output terminal 110. Circuit 103, on the other hand, reads out the test pattern of a word from circuit 104 and commands circuit 105 to send a signal from circuit 104 to circuit 107. Then, a right-answer value equivalent to the pattern is read out by circuit 106 and compared by circuit 108, so that they agree, the display of a test end will be done at terminal 111.
COPYRIGHT: (C)1979,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14753777A JPS5479569A (en) | 1977-12-07 | 1977-12-07 | Intergrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14753777A JPS5479569A (en) | 1977-12-07 | 1977-12-07 | Intergrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5479569A true JPS5479569A (en) | 1979-06-25 |
Family
ID=15432547
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14753777A Pending JPS5479569A (en) | 1977-12-07 | 1977-12-07 | Intergrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5479569A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60124745A (en) * | 1983-12-09 | 1985-07-03 | Fujitsu Ltd | Logical simulation system |
JPS62214378A (en) * | 1986-03-15 | 1987-09-21 | Nippon Denso Co Ltd | Dynamic burn-in device for semiconductor integrated circuit |
JPS63153483A (en) * | 1986-12-17 | 1988-06-25 | Fujitsu Ltd | Semiconductor integrated circuit |
JPH06242187A (en) * | 1993-02-12 | 1994-09-02 | Nec Corp | Semiconductor self test device |
-
1977
- 1977-12-07 JP JP14753777A patent/JPS5479569A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60124745A (en) * | 1983-12-09 | 1985-07-03 | Fujitsu Ltd | Logical simulation system |
JPS62214378A (en) * | 1986-03-15 | 1987-09-21 | Nippon Denso Co Ltd | Dynamic burn-in device for semiconductor integrated circuit |
JPS63153483A (en) * | 1986-12-17 | 1988-06-25 | Fujitsu Ltd | Semiconductor integrated circuit |
JPH06242187A (en) * | 1993-02-12 | 1994-09-02 | Nec Corp | Semiconductor self test device |
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