JPS5727041A - Large-scale integrated circuit having testing function - Google Patents

Large-scale integrated circuit having testing function

Info

Publication number
JPS5727041A
JPS5727041A JP10112180A JP10112180A JPS5727041A JP S5727041 A JPS5727041 A JP S5727041A JP 10112180 A JP10112180 A JP 10112180A JP 10112180 A JP10112180 A JP 10112180A JP S5727041 A JPS5727041 A JP S5727041A
Authority
JP
Japan
Prior art keywords
test
register
latch
designating
mode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10112180A
Other languages
Japanese (ja)
Other versions
JPS6331935B2 (en
Inventor
Shigeaki Yoshida
Yoshinori Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Renesas Eastern Japan Semiconductor Inc
Original Assignee
Hitachi Tokyo Electronics Co Ltd
Hitachi Ltd
Hitachi Ome Electronic Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Tokyo Electronics Co Ltd, Hitachi Ltd, Hitachi Ome Electronic Co Ltd filed Critical Hitachi Tokyo Electronics Co Ltd
Priority to JP10112180A priority Critical patent/JPS5727041A/en
Publication of JPS5727041A publication Critical patent/JPS5727041A/en
Publication of JPS6331935B2 publication Critical patent/JPS6331935B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor

Abstract

PURPOSE:To work the testing function effectively without attaching a terminal for a test by mounting a latch-register designating a test-mode and a reset inputting means to the LSI. CONSTITUTION:The latch-register 12 designating the test-mode is set up into the LSI10 having the testing function or one part of a register 11 for control previously built in is utilized as the latch-register 12 designating the test-mode while a data input terminal group Pi and a reset terminal-RES are fitted and the latch-register 12 designating the test-mode is set through an external data-but 13 from a tester of a CPU, etc. only when reset input is active. Accordingly, an external pin is unnecessitated because the latch-register designating the test-mode can be set by signals from the data-bus in place of signals from the external pin for the test.
JP10112180A 1980-07-25 1980-07-25 Large-scale integrated circuit having testing function Granted JPS5727041A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10112180A JPS5727041A (en) 1980-07-25 1980-07-25 Large-scale integrated circuit having testing function

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10112180A JPS5727041A (en) 1980-07-25 1980-07-25 Large-scale integrated circuit having testing function

Publications (2)

Publication Number Publication Date
JPS5727041A true JPS5727041A (en) 1982-02-13
JPS6331935B2 JPS6331935B2 (en) 1988-06-27

Family

ID=14292236

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10112180A Granted JPS5727041A (en) 1980-07-25 1980-07-25 Large-scale integrated circuit having testing function

Country Status (1)

Country Link
JP (1) JPS5727041A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58222500A (en) * 1982-04-20 1983-12-24 マステク・コ−パレイシヤン Starting of select mechanism
JPS6356741A (en) * 1986-08-28 1988-03-11 Nec Corp Test circuit
JPH0389182A (en) * 1989-08-31 1991-04-15 Sharp Corp Integrated circuit apparatus
JP2015156196A (en) * 2014-02-21 2015-08-27 株式会社デンソー microcomputer
CN110941218A (en) * 2019-12-10 2020-03-31 北京振兴计量测试研究所 CAN bus controller test method

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5264749U (en) * 1975-11-07 1977-05-13
JPS56162849A (en) * 1980-05-20 1981-12-15 Fujitsu Ltd Integrated circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5264749U (en) * 1975-11-07 1977-05-13
JPS56162849A (en) * 1980-05-20 1981-12-15 Fujitsu Ltd Integrated circuit

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58222500A (en) * 1982-04-20 1983-12-24 マステク・コ−パレイシヤン Starting of select mechanism
JPS6237480B2 (en) * 1982-04-20 1987-08-12 Mostek Corp
JPS6356741A (en) * 1986-08-28 1988-03-11 Nec Corp Test circuit
JPH0389182A (en) * 1989-08-31 1991-04-15 Sharp Corp Integrated circuit apparatus
JP2015156196A (en) * 2014-02-21 2015-08-27 株式会社デンソー microcomputer
CN110941218A (en) * 2019-12-10 2020-03-31 北京振兴计量测试研究所 CAN bus controller test method
CN110941218B (en) * 2019-12-10 2021-02-26 北京振兴计量测试研究所 CAN bus controller test method

Also Published As

Publication number Publication date
JPS6331935B2 (en) 1988-06-27

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