JPS55128168A - Testing method of memory in chip - Google Patents
Testing method of memory in chipInfo
- Publication number
- JPS55128168A JPS55128168A JP3669679A JP3669679A JPS55128168A JP S55128168 A JPS55128168 A JP S55128168A JP 3669679 A JP3669679 A JP 3669679A JP 3669679 A JP3669679 A JP 3669679A JP S55128168 A JPS55128168 A JP S55128168A
- Authority
- JP
- Japan
- Prior art keywords
- latch
- scan
- memory
- data
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
PURPOSE: To prevent change in the scan-in data and simplify the testing with a double construction of the latch around the memory.
CONSTITUTION: A memory is tested in the chip having a logic circuit and the memory mixed by the scan-in/scan-out system. In this case, a part or the whole of a data retaining equipment block around the memory cell is composed of a front stage latch 23, a multiplexer adapted to select a signal from the latch 23 and a signal Sn from the logic circuit and a rear stage latch 15. In the test mode, scan/in data is set at the latch 15 through the latch 23 and the multiplexer 24. Thus, the change in the scan-in data can be prevented.
COPYRIGHT: (C)1980,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3669679A JPS55128168A (en) | 1979-03-28 | 1979-03-28 | Testing method of memory in chip |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3669679A JPS55128168A (en) | 1979-03-28 | 1979-03-28 | Testing method of memory in chip |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS55128168A true JPS55128168A (en) | 1980-10-03 |
Family
ID=12476940
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3669679A Pending JPS55128168A (en) | 1979-03-28 | 1979-03-28 | Testing method of memory in chip |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS55128168A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02298877A (en) * | 1989-03-13 | 1990-12-11 | Fujitsu Ltd | Method for forming automatic test circuit of integrated circuit |
KR100318445B1 (en) * | 1998-06-30 | 2002-02-19 | 박종섭 | Device and method for testing internal memory in semiconductor chip |
JP2018137024A (en) * | 2017-02-21 | 2018-08-30 | 株式会社東芝 | Semiconductor integrated circuit |
-
1979
- 1979-03-28 JP JP3669679A patent/JPS55128168A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02298877A (en) * | 1989-03-13 | 1990-12-11 | Fujitsu Ltd | Method for forming automatic test circuit of integrated circuit |
KR100318445B1 (en) * | 1998-06-30 | 2002-02-19 | 박종섭 | Device and method for testing internal memory in semiconductor chip |
JP2018137024A (en) * | 2017-02-21 | 2018-08-30 | 株式会社東芝 | Semiconductor integrated circuit |
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