JPS55107964A - Device for evaluation of integrated circuit - Google Patents

Device for evaluation of integrated circuit

Info

Publication number
JPS55107964A
JPS55107964A JP1520579A JP1520579A JPS55107964A JP S55107964 A JPS55107964 A JP S55107964A JP 1520579 A JP1520579 A JP 1520579A JP 1520579 A JP1520579 A JP 1520579A JP S55107964 A JPS55107964 A JP S55107964A
Authority
JP
Japan
Prior art keywords
circuit
integrated circuit
connecting data
magnetic tape
circuit connecting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1520579A
Other languages
Japanese (ja)
Other versions
JPS618973B2 (en
Inventor
Kanji Hirabayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CHIYOU LSI GIJUTSU KENKYU KUMIAI
CHO LSI GIJUTSU KENKYU KUMIAI
Original Assignee
CHIYOU LSI GIJUTSU KENKYU KUMIAI
CHO LSI GIJUTSU KENKYU KUMIAI
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CHIYOU LSI GIJUTSU KENKYU KUMIAI, CHO LSI GIJUTSU KENKYU KUMIAI filed Critical CHIYOU LSI GIJUTSU KENKYU KUMIAI
Priority to JP1520579A priority Critical patent/JPS55107964A/en
Publication of JPS55107964A publication Critical patent/JPS55107964A/en
Publication of JPS618973B2 publication Critical patent/JPS618973B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Tests Of Electronic Circuits (AREA)
  • Detection And Correction Of Errors (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

PURPOSE: To check a circuit operation of an integrated circuit by applying a mask fabricating magnetic tape for the integrated circuit and test series for input signal terminals to automatically simulate the circuit.
CONSTITUTION: A mask fabricating magnetic tape 51 is first inputted to a pattern analyzer 52, which forms the circuit connecting data of transistor level 60. Then, the circuit connecting data of gate level 61 are formed on the basis of the circuit connecting data of the transistor level 60 obtained at the analyzer 52 by a gate recognition unit 53. Then, the circuit connecting data of the gate level 61 and the test series 63 for the input signal terminals are applied to a logic simulator 54. A comparator 55 compares the output 62 from the simulator 54 with the expected output 64. Thus, a logic simulation is automatically performed on the basis of the mask fabricating magnetic tape to check the operation of the integrated circuit.
COPYRIGHT: (C)1980,JPO&Japio
JP1520579A 1979-02-13 1979-02-13 Device for evaluation of integrated circuit Granted JPS55107964A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1520579A JPS55107964A (en) 1979-02-13 1979-02-13 Device for evaluation of integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1520579A JPS55107964A (en) 1979-02-13 1979-02-13 Device for evaluation of integrated circuit

Publications (2)

Publication Number Publication Date
JPS55107964A true JPS55107964A (en) 1980-08-19
JPS618973B2 JPS618973B2 (en) 1986-03-19

Family

ID=11882360

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1520579A Granted JPS55107964A (en) 1979-02-13 1979-02-13 Device for evaluation of integrated circuit

Country Status (1)

Country Link
JP (1) JPS55107964A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4744084A (en) * 1986-02-27 1988-05-10 Mentor Graphics Corporation Hardware modeling system and method for simulating portions of electrical circuits

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6123275U (en) * 1984-07-18 1986-02-12 矢崎総業株式会社 waterproof connector

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4744084A (en) * 1986-02-27 1988-05-10 Mentor Graphics Corporation Hardware modeling system and method for simulating portions of electrical circuits

Also Published As

Publication number Publication date
JPS618973B2 (en) 1986-03-19

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