JPS5651677A - Testing method - Google Patents

Testing method

Info

Publication number
JPS5651677A
JPS5651677A JP12685579A JP12685579A JPS5651677A JP S5651677 A JPS5651677 A JP S5651677A JP 12685579 A JP12685579 A JP 12685579A JP 12685579 A JP12685579 A JP 12685579A JP S5651677 A JPS5651677 A JP S5651677A
Authority
JP
Japan
Prior art keywords
signal
pattern
observed
test
logic circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12685579A
Other languages
Japanese (ja)
Inventor
Yoshimitsu Takiguchi
Yuichi Oka
Kiyoshi Numata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP12685579A priority Critical patent/JPS5651677A/en
Publication of JPS5651677A publication Critical patent/JPS5651677A/en
Pending legal-status Critical Current

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  • Tests Of Electronic Circuits (AREA)

Abstract

PURPOSE: To make it possible to make tests of variety by previously determining, pattern by pattern, whether an external terminal connected to input and output pins is applied with a signal or observed in a test and by making a test according to the determination.
CONSTITUTION: Interface 31 receives previously set-up test patterns and control information showing whether a terminal with input and output pins is applied with a signal or observed, and controller 32 controls the whole device and also compares the actual signal value of tested logic circuit 38 sent from receiver 36 to a preset expected signal to decide on rejection and acceptance. Table 33 is stored with pattern-by-pattern control signals showing whether the external terminal is applied with the signal or observed, and table 34 with test patterns to be supplied to tested logic circuit 38.
COPYRIGHT: (C)1981,JPO&Japio
JP12685579A 1979-10-03 1979-10-03 Testing method Pending JPS5651677A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12685579A JPS5651677A (en) 1979-10-03 1979-10-03 Testing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12685579A JPS5651677A (en) 1979-10-03 1979-10-03 Testing method

Publications (1)

Publication Number Publication Date
JPS5651677A true JPS5651677A (en) 1981-05-09

Family

ID=14945508

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12685579A Pending JPS5651677A (en) 1979-10-03 1979-10-03 Testing method

Country Status (1)

Country Link
JP (1) JPS5651677A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5844366A (en) * 1981-09-10 1983-03-15 Fujitsu Ltd Large-scale integrated circuit with reentry pin
JPH04365711A (en) * 1991-06-11 1992-12-17 Nitto Seiko Co Ltd Parts take-out device
JPH0633819U (en) * 1992-03-16 1994-05-06 車体工業株式会社 Part take-out mechanism in assembly parts quantitative feeder

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5844366A (en) * 1981-09-10 1983-03-15 Fujitsu Ltd Large-scale integrated circuit with reentry pin
JPH04365711A (en) * 1991-06-11 1992-12-17 Nitto Seiko Co Ltd Parts take-out device
JPH0633819U (en) * 1992-03-16 1994-05-06 車体工業株式会社 Part take-out mechanism in assembly parts quantitative feeder

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