JPS56150367A - Tester for logic circuit - Google Patents

Tester for logic circuit

Info

Publication number
JPS56150367A
JPS56150367A JP5388680A JP5388680A JPS56150367A JP S56150367 A JPS56150367 A JP S56150367A JP 5388680 A JP5388680 A JP 5388680A JP 5388680 A JP5388680 A JP 5388680A JP S56150367 A JPS56150367 A JP S56150367A
Authority
JP
Japan
Prior art keywords
pattern
input
output
stored
register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5388680A
Other languages
Japanese (ja)
Inventor
Toshishige Ando
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP5388680A priority Critical patent/JPS56150367A/en
Publication of JPS56150367A publication Critical patent/JPS56150367A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits

Abstract

PURPOSE:To make hardware constitution less intricate by providing input-output circuits of variable input and output and a shift register and outputting an anticipated pattern serially from the object to be tested on the basis of the test pattern inputted serially. CONSTITUTION:A control circuit 20 transmits a prescribed test pattern P from a memory 10 to an object 40 to be tested via a shift register 30. The pattern P is once stored in a register 30. The register 30 is provided with the input-output circuits that permit changing input and output arbitrarily on the basis of the input-output terminals of the object 40, and the input-output circuits are operated by the input- output setting pattern WP having been stored in the shift register 50. The output pattern having been stored in the register 30 is stored into FF0-FFn where the object 40 is shift-registered; at the same time, the previously stored scan pattern is outputted into a circuit 20. The stored pattern and scan pattern are checked whether they are prescribed patterns or not in the circuit 20.
JP5388680A 1980-04-23 1980-04-23 Tester for logic circuit Pending JPS56150367A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5388680A JPS56150367A (en) 1980-04-23 1980-04-23 Tester for logic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5388680A JPS56150367A (en) 1980-04-23 1980-04-23 Tester for logic circuit

Publications (1)

Publication Number Publication Date
JPS56150367A true JPS56150367A (en) 1981-11-20

Family

ID=12955210

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5388680A Pending JPS56150367A (en) 1980-04-23 1980-04-23 Tester for logic circuit

Country Status (1)

Country Link
JP (1) JPS56150367A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6010186A (en) * 1983-06-30 1985-01-19 Fujitsu Ltd Generation of test pattern

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6010186A (en) * 1983-06-30 1985-01-19 Fujitsu Ltd Generation of test pattern

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