JPS5661663A - Testing device of logic circuit - Google Patents

Testing device of logic circuit

Info

Publication number
JPS5661663A
JPS5661663A JP13746379A JP13746379A JPS5661663A JP S5661663 A JPS5661663 A JP S5661663A JP 13746379 A JP13746379 A JP 13746379A JP 13746379 A JP13746379 A JP 13746379A JP S5661663 A JPS5661663 A JP S5661663A
Authority
JP
Japan
Prior art keywords
signal
test
output
timing
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13746379A
Other languages
Japanese (ja)
Inventor
Yasushi Matsukawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP13746379A priority Critical patent/JPS5661663A/en
Publication of JPS5661663A publication Critical patent/JPS5661663A/en
Pending legal-status Critical Current

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  • Tests Of Electronic Circuits (AREA)

Abstract

PURPOSE: To make possible to change the conventional test in two times into the test in one operation to improve the test efficiency by combining every two systems among plural systems having voltage comparing circuits and comparing circuits.
CONSTITUTION: A tested output signal applied to a terminal 21 is compared with a standard voltage 31 by a voltage comparing circuit 11, the signal thus converted into a logic signal 41 enters a logic comparing circuit 51 via a selecting circuit 91 and is judged by test information 61 set in a test pattern and the timing of a preset judging timing signal 71, and a resulting good or bad signal 81 is output. On the other hand, the output 41 of the voltage comparing circuit 11 is selected by a preset selection signal 10' in a selecting circuit 92, input to a logic comparing circuit 52, judged by expected information 62 set in the test pattern and the timing of a judging timing signal 72, and a resulting good or bad signal 82 is output. A tested output signal to an input terminal 22 is processed in the same way.
COPYRIGHT: (C)1981,JPO&Japio
JP13746379A 1979-10-24 1979-10-24 Testing device of logic circuit Pending JPS5661663A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13746379A JPS5661663A (en) 1979-10-24 1979-10-24 Testing device of logic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13746379A JPS5661663A (en) 1979-10-24 1979-10-24 Testing device of logic circuit

Publications (1)

Publication Number Publication Date
JPS5661663A true JPS5661663A (en) 1981-05-27

Family

ID=15199186

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13746379A Pending JPS5661663A (en) 1979-10-24 1979-10-24 Testing device of logic circuit

Country Status (1)

Country Link
JP (1) JPS5661663A (en)

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