JPS5562373A - Logic circuit test unit - Google Patents

Logic circuit test unit

Info

Publication number
JPS5562373A
JPS5562373A JP13534478A JP13534478A JPS5562373A JP S5562373 A JPS5562373 A JP S5562373A JP 13534478 A JP13534478 A JP 13534478A JP 13534478 A JP13534478 A JP 13534478A JP S5562373 A JPS5562373 A JP S5562373A
Authority
JP
Japan
Prior art keywords
circuit
quality
logic
output data
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13534478A
Other languages
Japanese (ja)
Inventor
Hiroshi Nozaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Usac Electronic Ind Co Ltd
Original Assignee
Usac Electronic Ind Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Usac Electronic Ind Co Ltd filed Critical Usac Electronic Ind Co Ltd
Priority to JP13534478A priority Critical patent/JPS5562373A/en
Publication of JPS5562373A publication Critical patent/JPS5562373A/en
Pending legal-status Critical Current

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  • Tests Of Electronic Circuits (AREA)

Abstract

PURPOSE: To realize the test for the logic circuit by having the selection between the CRC system or the counting system according to the logic value applied to the input, thus ensuring an accurate decision for the quality of the tested card.
CONSTITUTION: In case the input to NOT circuit 8 is logic 0, the output data given from the tested card is given to input terminal TD of CRC circuit 5 via AND circuit 9 and OR circuit 13. At the same time the internal clock is supplied to input terminal TC via AND circuit 11 and OR circuit 14. Then the contents of circuit 5 is compared with the expected value at the moment when the output data corresponding to the test data has been sent completely, thus giving the decision for the quality. While the fixed signal and the output data are supplied to terminal TD and terminal TC via circuits 10 and 13 plus circuits 12 and 14 respectively. As a result, the value of shift register 7 features the function of the transition number, and the contents of circuit 5 is compared with the expected value to decide the quality of the card.
COPYRIGHT: (C)1980,JPO&Japio
JP13534478A 1978-11-02 1978-11-02 Logic circuit test unit Pending JPS5562373A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13534478A JPS5562373A (en) 1978-11-02 1978-11-02 Logic circuit test unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13534478A JPS5562373A (en) 1978-11-02 1978-11-02 Logic circuit test unit

Publications (1)

Publication Number Publication Date
JPS5562373A true JPS5562373A (en) 1980-05-10

Family

ID=15149574

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13534478A Pending JPS5562373A (en) 1978-11-02 1978-11-02 Logic circuit test unit

Country Status (1)

Country Link
JP (1) JPS5562373A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5746170A (en) * 1980-09-05 1982-03-16 Hitachi Ltd Device for testing logic circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5746170A (en) * 1980-09-05 1982-03-16 Hitachi Ltd Device for testing logic circuit
JPS6318709B2 (en) * 1980-09-05 1988-04-19 Hitachi Ltd

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