JPS63250743A - Test mode setting system - Google Patents

Abstract

PURPOSE:To set up a test mode when a reset signal is valid and a read timing signal is in an 'L' level by inputting a read clock and inputting an 'H' level signal from the output of an FF to a signal processing processor. CONSTITUTION:A read timing signal (b) is inverted by a NOT circuit 3 and inputted to an input terminal D of the FF 2, a read clock (c) is inputted to a clock terminal CLK and a reset signal (a) is inputted to a clear terminal CLR. If the read clock (c) which is nor usually inputted is inputted when both the reset signal (a) and read timing signal (b) are in the 'L' levels, the output (d) of the FF 2 is turned to the 'H' level. Consequently, a signal processor 1 is turned to the test mode to execute tests.

Description

[Detailed Description of the Invention] [Summary] In order to prevent the signal processing processor LSI from falling into test mode due to noise etc. when it is in normal execution mode and going into a runaway state where it cannot automatically return to normal execution mode, test For the flip-flop that outputs the mode signal, input the read timing signal inverted by a NOT circuit to the input terminal, input the read clock to the clock terminal, and input the reset signal to the clear terminal. By doing this, when the reset signal is valid, the test mode is set, and when the reset signal is released, that is, the flip-flop is in the clear state, and the output is not in the test mode at H level due to noise etc., the normal execution mode is set. This is what I did.

[Industrial application field]

The present invention relates to an improvement in a test mode setting method for setting a signal processing processor in a test mode for a signal processing processor LSI used in communication equipment, electronic equipment, etc.

The signal processing processor LSI operates as a program-controlled processor, and the mask RO inside the LSI
In most cases, it is operated by a program stored in M.

However, in order to test this LSI, a test-specific program is externally input into RAM and operated, so the signal processing processor is forced to enter normal execution mode (mask ROM).
In addition to the programmatic operation), a test mode is also required.

It is desired that the test mode setting method for switching to this test mode be such that the normal execution mode does not change to the test mode due to internal disturbances in the LSI.

[Conventional technology]

A conventional example will be explained below using figures.

Fig. 3 is a block diagram of the main parts of a conventional signal processing processor LSI, Fig. 4 is a time chart of waveforms of each part when the test mode is set in Fig. 3, and Fig. 5 is a block diagram of the main parts of a conventional signal processing processor LSI. 3 is a waveform time chart showing a case where the normal execution mode changes to the test mode.

Conventionally, the input terminal of the flip-flop 2 which outputs the test mode signal is inputted with the read timing signal inverted by the knot circuit 3, the clock terminal is inputted with the cent signal, and the output is inputted. The test mode signal is output.

In this way, as shown in Fig. 4 (A) (when releasing the reset signal, if the read timing signal is set to L level as shown in (B), the output will be at H level as shown in (C)). A test mode signal is output, and the signal processor 1 is placed in the test mode.

Also, when the read timing signal shown in (B) is at H level (
When the reset signal is released as shown in A), the output of the flip-flop 2' becomes L level as shown in (C).
It becomes normal execution mode.

This is how you put it into test mode.

[Inventiveness' Problems that JW is trying to solve] However,
Since this flip-flop 2' is inside the LSI, the 5th flip-flop
As shown in the figure, due to disturbances such as noise in the normal execution mode, when the read timing signal is at the L level as shown in Figures 5 (A) and (B), the reset signal goes to the L level and becomes H.
When something happens that becomes a level, it goes into test mode.

Once in test mode, it does not automatically return to normal execution mode and becomes out of control.

As mentioned above, the conventional test mode setting method has a problem in that it may become out of control.

To return to the normal execution mode, as shown in FIG. 4, when the read timing signal is at H level, the reset signal is enabled (L level) and released (H level).

[Means for solving problems]

FIG. 1 is a block diagram of the main parts of a signal processing processor LSI according to an embodiment of the present invention.

In order to put the signal processor 1 into the test mode, the input terminal of the flip-flop 2 that outputs the test mode signal is inverted with the read timing signal by the knot circuit 3, and the read timing signal is input to the clock terminal. input, and the clear terminal is input with a cent signal.

In this way, when entering the test mode, when the reset signal is valid (L level) and the read timing signal is L level, the read clock is input and the output of flip-flop 2 is set to 1 (level 1). The signal is outputted and inputted to the signal processing processor 1.

[Effect]

According to the present invention, when entering the test mode, when the reset signal is valid (L level) and the read timing signal is L level, the read clock is inputted, and the output of the flip-flop 2 is input with an H level signal. output.

Next, when entering the normal execution mode, by canceling the recent signal (high level), the flip-flop 2 is cleared, the output becomes low level, and the normal execution mode is entered.

That is, the output of flip-flop 1 can be set to H level only when the reset signal is valid, making it possible to enter test mode. In normal execution mode, the reset signal is at L level and flip-flop 2 is in a clear state. , LSI
Even if there is a disturbance internally, the output of flip-flop 2 remains H.
It can be a level, it can never be a test mode.

Therefore, even if disturbances such as noise occur inside the LSI,
It will not enter test mode during normal execution mode and will not run out of control.

In order to continue the reset state, the read timing signal and read clock are in the normal state.When the read timing signal is at H level, the read clock is input, and when the read timing signal is at L level, the read clock is input. It is best to avoid inputting .

〔Example〕

An embodiment of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 shows a signal processing bromo nosa according to an embodiment of the present invention.
- A block diagram of the main parts of the LSI, Figure 2 is a time chart of the waveforms of each part in Figure 1, and (A) to l) are the a w of Figure 1.
It corresponds to point d.

In Fig. 1, the read timing signal is inverted and inputted to the input terminal of the flip-flow knob 1 which emits an H-level test mode signal as shown in Fig. 2 (D>) and the node circuit 3. A read clock is input to the clock terminal, and a reset signal is manually input to the clear terminal.

By doing this, when the reset signal is at the L level as shown in FIG. 2 (A) and the read timing signal is at the L level as shown in FIG. 2 (B) (usually no read clock is input at this time) (C ) When the read clock is inputted as shown in (D), the output of the flip-flop 2 becomes H level as shown in (D), and the signal processing processor 1 enters the test mode and performs a test.

Next, as shown in (A), when the reset signal is set to H level (released), the flip-flop 2 becomes a clear state, and the output becomes L level as shown in (D), entering the normal execution mode.

In this way, in the normal execution mode, the flip-flop 2 is in a clear state, so even if disturbances such as noise occur inside the LSI, the output will not go to H level and the test mode will not be entered.

Therefore, the normal execution mode becomes the test mode, and there is no possibility of a runaway state that does not automatically recover.

In order to continue the reset state, the read timing signal and read clock are in the normal state.When the read timing signal is at H level, the read clock is input, and when the read timing signal is at L level, the read clock is input. It is best to avoid inputting .

C. Effects of the Invention] As described above in detail, according to the present invention, in the normal execution mode, the flip-flop 2 is in a clear state, so even if disturbances due to noise etc. occur inside the signal processing processor LSI, the output will not be affected. It does not go to H level and does not enter test mode (it becomes test mode during normal execution mode, which has the effect of preventing a runaway state that does not automatically recover).

[Brief explanation of drawings]

FIG. 1 is a block diagram of the main parts of a signal processing processor LSI according to an embodiment of the present invention, FIG. 2 is a time chart of waveforms of each part in FIG. 1, and FIG. 3 is a main part of a conventional signal processing processor LSI. Figure 4 is a time chart of the waveforms of each part when switching to test mode in Figure 3. Figure 5 shows the case where the mode is changed from normal execution mode to test mode due to disturbance in Figure 3. This is a waveform time chart. In the figure, ① indicates processor No. 13, 2.2' indicates a flip-flow knob, and 3 indicates a knot circuit. k! ? 5 Figure 1 test mode 13ゐ, 8 block p of 5 friends

Claims (1)

[Claims] In order to put the signal processing processor (1) into test mode,
The read timing signal is connected to the input terminal of the flip-flop (2) that outputs the test mode signal.
), the read clock is input to the clock terminal, and the reset signal is input to the clear terminal. When the reset signal is valid and the read timing signal is at L level, A test mode setting method characterized in that a read clock is input and an H level signal is output from the output of the flip-flop (2) to set the test mode.