JPH06138191A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To perform the functional test of blocks to be tested without providing an exclusive pin for the test in a semiconductor integrated circuit with a self-test circuit in a chip. CONSTITUTION:A power-on reset circuit 1 is provided in a chip and at the same time an output TST1 of a D-type flip-flop 2 with a power-on reset signal as a clock input and a system clock as data input is led to a multiplexer 4 at the pre-stage of a specific block 11 to be tested via a matrix circuit 3. A normal signal and a test signal are input to the multiplexer 4 and either of the input signals is switched and output according to a selection signal SEL based on the flip-flop output TST 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit formed by forming a self-test circuit in a chip, and more particularly to a large-scale semiconductor integrated circuit having a switching means between a test mode and a normal mode and a selecting means for a test object. (LSI, the same applies hereinafter).

[0002]

2. Description of the Related Art In LSI, it is common to perform a functional test on a chip mounting block at the time of shipping or mounting. Further, for a block in which a failure is difficult to detect, in order to facilitate test pattern generation, a multiplexer is added to the input / output side of the block to form a self-test circuit so that the block can be directly accessed from outside the chip.

FIG. 4 is a basic configuration diagram of this type of self-test circuit. 10 is a first multiplexer, 11 is a block to be tested, 12 is another chip mounting block, 13 is a second multiplexer, and 14 is an input. A buffer, 15 is a test buffer, 16 is an output buffer, and 17 is an external connection pin.

The first multiplexer 10 has a normal mode signal (data signal) directly from the outside of the chip or from another block in the chip and an input buffer 14.
And the test mode signal derived from the
Either one of the two mode signals is selected by TST and is input to the test target block 11. This test switching signal TS
T is also input to the second multiplexer 13 and is selectively switched in synchronization with the first multiplexer 10.

When the normal mode is selected, the output of the test target block 11 is led to the external buffer 16 via the other block 12 and the second multiplexer 13. On the other hand, when the test mode is selected, the output of the block under test 11 is guided to the external buffer 16 via the second multiplexer 13. In the illustrated example, when the test switching signal TST is the "1" signal (High signal), the test mode is "0" (Lo signal).
w signal), the normal mode is entered.

[0006]

As described above, the prior art is as follows.
In order to facilitate the generation of the test pattern, multiplexers 10 and 13 are added to the input / output side of the test target block 11 at the portion where the failure detection is difficult to form a self-test circuit so that the portion can be directly accessed from outside the chip. I was doing. However, in the self-test circuit configured as described above, it is necessary to provide the pin 17 for inputting the test switching signal TST exclusively for the test, which is an overhead in LSI design. In particular, it was a very big problem for products with limited number of pins.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor integrated circuit having a structure which does not require a test-dedicated pin.

[0008]

In order to achieve the above object, the present invention uses a system clock for operation management of a semiconductor integrated circuit for switching between test modes, and
A data signal input from the outside of the chip was used to select a plurality of blocks to be tested.

That is, the first structure of the present invention is that the self-test circuit having the test target block and the mode switching means for switching the operation mode of the test target block to either the normal mode or the test mode is provided in the chip. And a signal generation circuit such as a power-on reset circuit that generates a reset signal that becomes active when the power is turned on.
A flip-flop (hereinafter, abbreviated as F / F) that receives a reset signal as a clock input and a system clock input from the outside as a data input, and outputs a binary signal corresponding to the system clock level at the time of inputting the reset signal,
It includes a multiplexer for inputting the normal mode signal and the test mode signal and switching one of these input signals by the output of the F / F for output.

A second configuration of the present invention is that a plurality of test target blocks, a test target selecting means for selecting a specific test target block, and an operation mode of the selected test target block are a normal mode and a test mode. A semiconductor integrated circuit having a self-test circuit having a mode switching means for switching to either one of the above, in a chip, wherein the test target selecting means is a power-on circuit that generates a reset signal that becomes active when the power is turned on. A signal generation circuit such as a reset circuit and an F / F that outputs a binary signal corresponding to the system clock level at the time of inputting the reset signal, using the reset signal as a clock input, and the externally input system clock as a data input And a specific block to be tested is supported by combining at least two external data signals A mode switching means for inputting a normal mode signal and a test mode signal, and a matrix circuit for deciding the logical condition of the activated address output and the F / F output. And a multiplexer for switching and outputting either one of the input signals by the matrix circuit output.

[0011]

In both the first and second configurations, the output level of the F / F is determined by the system clock level when the reset signal output from the signal generating circuit is input. This reset signal is active only when the power is turned on.
The output level of the F / F continues until the next reset signal becomes active.

In the first configuration, the output of this F / F is used as the switching signal between the test mode and the normal mode. For example, when the test mode is selected, the binary signal level corresponding to the system clock level at power-on is set, and the F / F output at this time is guided to the multiplexer. As a result, the semiconductor integrated circuit enters the test mode and the functional test of the test target block becomes possible.

In the second configuration, by inputting at least two external data signals to the matrix circuit, the address corresponding to the specific test target block is made active, and the activated address and the F / F are added. The output of the multiplexer for the block to be tested is switched by determining the logical condition with the output. Therefore, even when a plurality of blocks to be tested are formed, the functional test of each block can be performed.

[0014]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention.
The example of the input side structure of a self-test circuit is shown. It is assumed that a plurality of blocks to be tested and a multiplexer for switching their inputs are formed in the chip.

In this embodiment, in order to switch the mode of a specific test target block 11 (conventional product), a self-test circuit is constituted by including a power-on reset circuit 1, an F / F 2, a matrix circuit 3 and a multiplexer 4. . Reference numeral 17 denotes an external connection pin (a component having the same function as the conventional one), which guides a chip external signal such as a system clock or external data into the chip via a buffer. Further, the test signal and the normal signal are input to the multiplexer 4 as in the conventional circuit.

The power-on reset circuit 1 has a power-on reset signal (hereinafter, referred to as a single pulse when the power is turned on).
A reset signal) is generated, and this reset signal is led to a clock input terminal of an F / F2 (D-type F / F, the same applies hereinafter). A system clock used as a clock of an on-chip mounted circuit is branched and input to the data input terminal of the F / F2. This system clock consists of a binary level pulse train, and its arrangement can be arbitrarily changed from outside the chip. In such a configuration, F / F2
Output level is determined by the system clock level when the reset signal is input. Since the reset signal becomes active only when the power is turned on, the output level of the F / F2 is maintained until the next reset signal becomes active. In this embodiment, the output of this F / F2 is used as a test switching signal.
Used as TST1.

The matrix circuit 3 specifies one block from a plurality of blocks to be tested, and a signal SEL for switching the test mode of the specified block.
Is a circuit for generating. The specific configuration is shown in FIG.
As shown in FIG. 5, the encoder 21 that makes an address corresponding to a specific test target block active by branching and inputting at least two external data signals (not shown)
And the activated address and the test switching signal TST1
And an AND gate 22 for determining an AND condition with. Selection signal SEL output from matrix circuit 3
Is guided to the multiplexer 4 and its output is switched.

Note that the above is an example of the configuration in the case where a plurality of blocks to be tested are formed, and the matrix circuit 3 is not necessarily required in the case of a single block. At this time, the output TST1 of the F / F2 is directly guided to the multiplexer 4.

FIGS. 3A and 3B are operation timing charts according to the above configuration. FIG. 3A shows an example of selecting the test mode and FIG. 3B shows an example of selecting the normal mode. Referring to these figures, by switching the system clock level at the time of starting the power-on reset circuit 1 to one of the binary levels, the binary level of the test switching signal TST1 corresponds to the binary level. Has become. That is,
As shown in FIG. 3 (a), by setting the system clock level to "High" at power-on, the entire chip is in the test mode, while as shown in FIG. 3 (b), at power-on, Set the system clock level to "Low"
By setting the above, the entire chip can be operated in the normal mode.

Therefore, by switching the output of the multiplexer 4 by using the test switching signal TST1, it becomes possible to switch between the test mode and the normal mode without providing a test-dedicated pin.

In this embodiment, the test switching signal TST1
Although the D-type F / F for outputting is used, it goes without saying that another type of F / F having the same function can be substituted.

[0023]

As described above, according to the present invention, the signal generation circuit is formed inside the chip, the reset signal is used as the clock input, and the system clock is used as the data input. Since the switching is performed, the test mode can be switched without increasing the number of test-dedicated pins as in the conventional case. In the case of a semiconductor integrated circuit, addition of an electronic circuit is extremely easy and cheap, but it is extremely difficult from the technical and cost point of view to save pins, and therefore, the effect of the present invention is extremely large. There is something like this.

[Brief description of drawings]

FIG. 1 is a basic configuration diagram of a self-test circuit in an LSI according to an embodiment of the present invention.

FIG. 2 is a specific configuration diagram of a matrix circuit used in this embodiment.

3A is a diagram showing an operation timing when a test mode is selected according to the present embodiment, and FIG. 3B is a diagram showing an operation timing when a normal mode is selected.

FIG. 4 is a basic configuration diagram of a conventional self-test circuit in an LSI.

[Explanation of symbols]

1 ... Power-on reset circuit (signal generation circuit), 2 ... Flip-flop, 3 ... Matrix circuit, 4, 10, 13
... multiplexer, 11 ... block to be tested 17 ... pin for external connection.

Continuation of the front page (51) Int.Cl. ⁵ Identification number Office reference number FI technical display location H01L 27/04 M 8427-4M

Claims (2)

[Claims] 1. A semiconductor integrated circuit in which a self-test circuit having a block to be tested and a mode switching means for switching an operation mode of the block to be tested to either a normal mode or a test mode is formed in a chip. The mode switching means includes a signal generation circuit that generates a reset signal that becomes active when the power is turned on, the reset signal as a clock input, and a system clock input from the outside as a data input, and when the reset signal is input. A flip-flop that outputs a binary signal corresponding to a system clock level, and a multiplexer that inputs a normal mode signal and a test mode signal and that switches one of these input signals by the output of the flip-flop and outputs the same. Semiconductor integrated circuit characterized by including . 2. A plurality of test target blocks, a test target selecting means for selecting a specific test target block, and a mode switching means for switching an operation mode of the selected test target blocks to either a normal mode or a test mode. A semiconductor integrated circuit having a self-test circuit having: formed in a chip, wherein the test target selection means includes a signal generation circuit that generates a reset signal that becomes active when power is turned on, and a clock signal that inputs the reset signal. With a system clock input from the outside as the data input and a flip-flop that outputs a binary signal corresponding to the system clock level at the time of reset signal input, and a combination of at least two external data signals The corresponding address output is made active and And a matrix circuit for determining a logical condition between the output of the address and the output of the flip-flop, and the mode switching means inputs a normal mode signal and a test mode signal, and one of these input signals. A semiconductor integrated circuit comprising: a multiplexer for switching and outputting according to the matrix circuit output.