JPH07151825A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To easily make a test by reducing the test-pattern generation time and the test time and without a need for a terminal exclusively used for the test. CONSTITUTION:The semiconductor integrated circuit is provided with output buffers 13a, 13b, a reset terminal 15, an input terminal 16 and multiplexers 12a, 12b whose input sides are connected to an internal circuit 11 and the input terminal 16, whose output sides are connected to respective input sides of the output buffers 13a, 13b and in which the signal of the input terminal 16 or the signal of the internal circuit 11 is transmitted to the output side according to whether a system reset signal exists or not.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit in which DC level testing of an output buffer is facilitated.

[0002]

2. Description of the Related Art Conventionally, as a part of a test of a semiconductor integrated circuit, there is a test method for testing the DC level of a signal output to an output terminal via an output buffer of the semiconductor integrated circuit to judge whether the semiconductor integrated circuit is good or bad. Has been taken. As one of the test methods, a test pattern in which both the'H 'level and the'L' level are output to all output terminals is created in advance, and these patterns are applied to the semiconductor integrated circuit to make all of them. Has been proposed for testing the DC level of the signal output to the output terminal of the. However, with the recent high integration of semiconductor integrated circuits, the test patterns have become complicated and the number of test patterns has become enormous, so that the test pattern generation time and the test time both increase, resulting in a burden on the test cost. Is increasing. Therefore, there has been proposed a method of testing the DC level of the signal output to the output terminal of the semiconductor integrated circuit without increasing the test pattern generation time and the test time. As one of them, for example, a test method as shown in FIG. 5 has been proposed.

FIG. 5 is a circuit diagram showing an input / output unit of a conventional semiconductor integrated circuit. To the DC mode terminal 51 '
When the L'level signal is input, each multiplexer 1
2a and 12b output the output signals of the internal circuit 11,
The output signals of the internal circuits output from the multiplexers 12a and 12b are output to the output terminals 14a and 14b via the output buffers 13a and 13b. On the other hand, when an'H 'level signal is input to the DC mode dedicated terminal 51, each multiplexer 12a, 12b outputs the signal input to the DC data dedicated terminal 52, and the multiplexer 1
The signals output from 2a and 12b are output buffer 13
It is output to each output terminal 14a, 14b via a, 13b. Therefore, the DC mode dedicated terminal 51 is set to "H".
While keeping the level, "H" is applied to the DC data dedicated terminal 52.
By checking the signals output to the output terminals 14a and 14b of the semiconductor integrated circuit by inputting the signals of the level and the'L 'level, the DC level test of the signals output from the output buffers 13a and 13b is executed. It

[0004]

In the conventional semiconductor integrated circuit shown in FIG. 5, the test of the output buffers 13a and 13b can be executed separately from the internal circuit 11. Therefore, the test pattern generation time and the test can be executed. Although the time is reduced, a test dedicated terminal such as a DC mode dedicated terminal 51 and a DC data dedicated terminal 52 is required. Therefore, in the case of a semiconductor integrated circuit to which all input / output terminals are assigned, it is impossible to provide these test-dedicated terminals.

In view of the above circumstances, it is an object of the present invention to provide a semiconductor integrated circuit in which a test pattern generation time and a test time are reduced and a test is facilitated without requiring a test-dedicated terminal. To do.

[0006]

According to a first semiconductor integrated circuit of the present invention which achieves the above object, (1) an output signal of an internal circuit arranged inside a semiconductor chip is transmitted to an output pin of the semiconductor chip. Output buffer (2) Reset terminal for inputting a system reset signal for initializing the internal circuit (3) Input terminal for input signal of the internal circuit (4) Input side is the internal circuit and the input terminal A multiplexer for transmitting the input signal or the output signal to the output side according to the presence / absence of the system reset signal. Is.

Further, the second semiconductor integrated circuit of the present invention for achieving the above object includes: (1) An output for transmitting an output signal of an internal circuit arranged inside a semiconductor chip to an output pin of the semiconductor chip. Buffer (2) Reset terminal to which a system reset signal for executing initialization of the internal circuit is input (3) Input terminal to which an input signal of the internal circuit is input (4) Reset state is released by input of the system reset signal A plurality of modes that output a mode identification signal that identifies at least three modes including the first mode at the time when the mode cyclically changes according to the input of the pulse signal from the input terminal and the reset state is released. (5) The input side is connected to the internal circuit and one of the plurality of mode identification terminals. The output side is connected to the input side of the output buffer, and the output side is connected to the input side of the output buffer, and the mode identification signal representing the first mode and the mode identification signals representing the two modes other than the first mode are respectively output. The present invention is characterized by including a multiplexer for transmitting to the output side an output signal and a signal representing one and the other of the logic levels output from one of the plurality of mode identifying terminals.

[0008]

According to the first semiconductor integrated circuit of the present invention, since the test signal is input to the reset terminal and the input terminal with the above-described configuration, an effective test can be performed without providing a test-dedicated terminal. . In addition, the second semiconductor integrated circuit of the present invention is provided with a test-dedicated terminal because the mode of the state machine is switched by the pulse signal input from the input terminal and the signal required for the test is output from the state machine. You can do a valid test without. Furthermore, since the signal of the internal circuit is output at the time when the system reset signal is input, when the semiconductor integrated circuit is initialized, the signal output from this semiconductor integrated circuit is uniquely determined. When designing a peripheral circuit of a semiconductor integrated circuit, the peripheral circuit can be initialized using an output signal at the time of initialization of the semiconductor integrated circuit.
For example, if the peripheral circuit is a motor drive circuit,
When the output signal at the time of initialization of the semiconductor integrated circuit is used as a signal for stopping the motor, an accidental accident such as sudden rotation of the motor at the time of initialization of the semiconductor integrated circuit is prevented.

[0009]

EXAMPLES Examples of the present invention will be described below. FIG. 1 is a circuit diagram showing a part of the circuit of an embodiment of the first semiconductor integrated circuit of the present invention. The circuit shown in this circuit diagram includes an internal circuit 11, two multiplexers 12a,
12b, two output buffers 13a, 13b, two input buffers 18a, 18b, two output terminals 14a, 1
4b, a reset terminal 15 and an input terminal 16.

The input terminal 16 has an internal circuit 11 and multiplexers 12a and 12b via an input buffer 18b.
Is connected to the input terminal '0'. The input terminal '1' of each multiplexer 12a, 12b is connected to the internal circuit 11
Connected with. Furthermore, each multiplexer 12a, 1
The output side of 2b is connected to the output terminals 14a and 14b via output buffers 13a and 13b.

A system reset signal for executing initialization of the internal circuit 11 is input to the reset terminal 15. The reset terminal 15 is connected to the internal circuit 11 and the multiplexers 12a and 12a via the input buffer 18a.
It is connected to the control terminal of b. Each input buffer 1
The output buffers 3a and 13b and the output buffers 18a and 18b are provided for protecting internal elements of the semiconductor integrated circuit and for matching with an external interface.

The "L" level of the system reset signal represents a system reset state in which the internal circuit is reset, and the "H" level represents an operating state in which the internal circuit is operated. When the signal of “H” level is input to the reset terminal 15, the signal of “H” level is transmitted to the internal circuit 11 via the input buffer 18a and brings the internal circuit 11 into an operating state. Further, this'H 'level signal is also input to the control terminals of the multiplexers 12a and 12b via the input buffer 18a.
Each of the multiplexers 12a and 12b transmits the signal input to the input terminal '1' to the output terminal, so that the signal of the internal circuit 11 on the input terminal '1' side is output from the output buffer 13
It is output to each output terminal 14a, 14b via a, 13b.

The signal input to the input terminal 16 is
It is transmitted to the internal circuit 11 via the input buffer 18b. Further, the signal input to the input terminal 16 is also input to the input terminal '0' of each of the multiplexers 12a and 12b. However, the reset terminal 15 indicates the operating state.
When the H'level is input, the signal input to the input terminal '0' is not transmitted to the output sides of the multiplexers 12a and 12b, and the multiplexers 12a and 12b output the internal circuit as described above. 11 output signals are output.

In this way, when the'H 'level signal is input to the reset terminal 15, the output signal of the internal circuit 11 is directly output to the output terminals 14a and 14b.
Further, the signal input to the input terminal 16 is also transmitted to the internal circuit 11 as it is, and thus the semiconductor integrated circuit is in a normal operation state. On the other hand, when an'L 'level signal for executing initialization is input to the reset terminal 15, this'L' level signal is input to the internal circuit 11 via the input buffer 18a, and the internal circuit 11 is initialized. Become.

One of the features of this embodiment is that the DC level test is executed by using the signals output to the output terminals 14a and 14b by utilizing the initialized state. That is, the'L 'level signal input to the reset terminal 15 is input to the control terminals of the multiplexers 12a and 12b via the input buffer 18a, whereby the multiplexers 12a and 12b are input to the input terminal' 0 '. The output signal 14a, 14b
Output to. Here, by sequentially inputting an “H” level signal and an “L” level signal as test data to the input terminal 16, signals corresponding to these input signals are output to the output terminals 14a and 14b. Therefore, the DC level can be tested by the signals output to the output terminals 14a and 14b.

FIG. 2 is a circuit diagram showing a part of the circuit of an embodiment of the second semiconductor integrated circuit of the present invention. In this circuit diagram, an internal circuit 11, two multiplexers 12a,
12b, two output buffers 13a and 13b, three input buffers 18a, 18b and 18c, a state machine 2
1, OR gate 22, two output terminals 14a, 14b,
Reset terminal 15, input terminal 16, and clock terminal 1
7 is shown.

The reset terminal 15 has an input buffer 18a.
Connected to the internal circuit 11 via the OR gate 2
It is also connected via 2 to a reset terminal of a state machine 21, which will be described later. The input terminal 16 is the input buffer 18
It is connected to the clock terminals of the internal circuit 11 and the state machine 21 via b. A clock terminal 17 for inputting a system clock signal is connected to the internal circuit 11 via an input buffer 18c and is connected to a reset terminal of the state machine 21 via an OR gate 22. The internal circuit 11 operates in synchronization with the system clock signal input to the clock terminal 17. Also,
The state machine 21 is reset by the'H 'level signal input to the reset terminal 15 and the'L' level signal of the system clock signal input to the clock terminal 17. In this embodiment, since the state machine is also reset by the system clock signal, even if an inadvertent pulse is applied to the clock terminal of the state machine 21 when the test pattern is switched,
The change of the state of the state machine 21 is prevented.

When the state machine 21 is in the reset state, both the mode "0" terminal and the mode "1" terminal of the state machine 21 output an "L" level signal. In addition, the state machine 21 has an input terminal 1
Depending on the number of pulses of the pulse signal input to 6, the mode '
The signals output to the 0'terminal and the mode '1' terminal are cyclically changed. Mode '0' terminal is each multiplexer 1
Connected to the input terminal '1' of 2a and 12b, and set to mode '
The 1'terminal is connected to the control terminal of each multiplexer 12a, 12b. In addition, each multiplexer 12a, 1
The input terminal '0' of 2b is connected to the internal circuit 11. As a result, each multiplexer 12a, 12b
When an "L" level signal is output to the mode "1" terminal, the output signal of the internal circuit 11 is output to the output terminals 14a and 14b, and when an "H" level signal is output to the mode "1" terminal. The output signal from the mode "0" terminal is output to the output terminal 14a,
Output to 14b.

The system reset state is released,
That is, when an "H" level signal indicating the operating state is input to the reset terminal 15, this "H" level signal is transmitted to the internal circuit 11 via the input buffer 18a to bring the internal circuit 11 into the operating state. . Further, the'H 'level signal resets the state machine 21 via the OR gate 22, and the'L' level signal is output to both the mode '0' terminal and the mode '1' terminal. Accordingly, the multiplexers 12a and 12b output the output signal of the internal circuit 11 to the output terminals 14a and 14b.

As described above, when the'H 'level signal is input to the reset terminal 15, the state machine 21 is held in the reset state and the output signal of the internal circuit 11 is output to the output terminals 14a and 14b. Is output. Further, the signal input to the input terminal 16 is also transmitted to the internal circuit 11, and the system clock signal input to the clock terminal 17 is also transmitted to the internal circuit 11, and this semiconductor integrated circuit is in a normal operating state.

When an "L" level signal for executing initialization is input to the reset terminal 15, this "L" level signal is input.
Level signal is passed through the input buffer 18a to the internal circuit 1
1 and the internal circuit 11 is initialized.
Further, when the reset terminal 15 changes to the'L 'level, the outputs of the mode' 0 'terminal and the mode' 1 'terminal of the state machine 21 are both at the'L' level, so that the output of the internal circuit 11 is Each output terminal 14a, 14
is output to b. This is one of the features of this embodiment, and as described above, this makes it possible to design a peripheral circuit that does not malfunction even if a system reset signal is input when the power is turned on.

When an "H" level signal is input to the clock terminal 17 and a pulse is sequentially input to the input terminal 16 while the "L" level signal is continuously input to the reset terminal 15, as will be described later, The signal output from the mode "1" terminal of the state machine 21 changes to the "H" level, and the "H" level and the "H" level are output from the output terminals 14a and 14b.
An L'level signal is output. As a result, the DC level test of the output signal is executed.

FIG. 3 is a diagram showing a cyclic change of the mode of the state machine 21 shown in FIG. A state in which the mode "0" terminal and the mode "1" terminal of the state machine 21 cyclically change will be described with reference to FIG. At the time when the signal of “L” level is input to the reset terminal 15, the mode “0” terminal and the mode terminal of the state machine 21 are
Both 1's are at the'L 'level and are in the mode' 00 'representing the normal state shown in FIG. Also, the internal circuit 1
1 (see FIG. 2) is initialized, and the output signal of the internal circuit 11 in the initialized state is output to each of the output terminals 14a and 14b.

When only one pulse is applied to the input terminal 16, the mode "0" terminal of the state machine 21 is "H".
Level, mode "1" terminal outputs "L" level signal, and mode "01" continues to indicate normal state
Therefore, the signal of the internal circuit 11 is also output to each of the output terminals 14a and 14b. When another pulse is applied to the input terminal 16, the mode of the state machine 21 becomes "0".
An "H" level signal is output to both the terminal and the mode "1" terminal, which indicates the DC1 state shown in FIG.
It becomes 1 '. In this case, the "H" level signal output to the mode "0" terminal is output from each output terminal 14a, 14a.
b. Another pulse on input terminal 16
When applied to the mode machine, an “L” level signal is output to the mode “0” terminal of the state machine 21, and the mode “1” is output.
An'H 'level signal is output to the terminal and D shown in FIG.
The mode becomes "10" which represents the state of C0. In this case, the "L" level signal output to the mode "0" terminal is transmitted to the output signals 14a and 14b. These four modes are cyclically repeated each time a pulse is applied, and in the DC1 mode and the DC0 mode, the signal output to the mode '0' terminal is output to each output terminal 14a, 14b, and each output terminal 14a, A DC level test of the signal output to 14b is performed.

FIG. 4 is a diagram showing a timing chart of the circuit shown in FIG. (A), (b), (c) are a reset signal applied to the reset terminal of the state machine 21, a pulse signal applied to the clock terminal of the state machine 21, and the output terminals 14a, 14 respectively.
The signal output to b is shown. When the reset signal shown in (a) is at the “H” level, the reset state of the internal circuit 11 is released, so the internal circuit 11 is in the normal operating state, while the state machine 21 is in the reset state. , The operation signal of the internal circuit 11 is directly output to the output terminals 14a and 14b. Next, when the reset signal changes to the'L 'level, the internal circuit 11 is initialized, while the state machine 21 exits the reset state and enters the mode' 00 'representing the normal state shown in FIG. 3 described above and initialized. The output signal of the internal circuit 11 is output. Next, when the first pulse shown in (b) is applied to the clock terminal of the state machine 21, the mode '01' representing the normal state shown in FIG.
Therefore, the output signal of the internal circuit 11 is output as it is. When a pulse is further applied, the rising edge of this pulse causes the mode 11 representing the DC state shown in FIG.
Then, the'H 'level signal is output to each of the output terminals 14a and 14b. When a pulse is further applied, the mode becomes the mode 10 showing the DC0 state shown in FIG.
An'L 'level signal is output to 4a and 14b. In this way, the DC level test of the output signals output to the output terminals 14a and 14b is executed.

[0026]

As described above, in the first semiconductor integrated circuit of the present invention, since the reset terminal and the input terminal are used as test terminals, a simple test pattern is provided without providing a dedicated test terminal. Effective testing can be performed, facilitating testing and reducing test cost.

The second semiconductor integrated circuit of the present invention is
Since the reset terminal, the input terminal, and the state machine are provided, an effective test can be performed with a simple pattern without providing a dedicated test terminal, which also simplifies the test and reduces the test cost. Further, since the signal of the internal circuit is output at the time of initialization, it is possible to prevent the peripheral circuit from performing an inadvertent operation.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a part of a circuit of an embodiment of a first semiconductor integrated circuit of the present invention.

FIG. 2 is a circuit diagram showing a part of a circuit of an embodiment of a second semiconductor integrated circuit of the present invention.

FIG. 3 is a diagram showing a cyclic change of modes of the state machine shown in FIG.

FIG. 4 is a diagram showing a timing chart of the circuit shown in FIG.

FIG. 5 is a circuit diagram showing a part of a conventional semiconductor integrated circuit.

[Explanation of symbols]

 11 Internal Circuit 12a, 12b Multiplexer 13a, 13b Output Buffer 14a, 14b Output Terminal 15 Reset Terminal 16 Input Terminal 17 Clock Terminal 18a, 18b, 18c Input Buffer 21 State Machine 22 OR Gate

Continuation of front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 21/822

Claims (2)

[Claims] 1. An output buffer for transmitting an output signal of an internal circuit arranged inside a semiconductor chip to an output pin of the semiconductor chip, and a reset terminal for receiving a system reset signal for executing initialization of the internal circuit. An input terminal to which an input signal of the internal circuit is input, an input side of which is connected to the internal circuit and the input terminal and an output side of which is connected to an input side of the output buffer, depending on the presence or absence of the system reset signal. And a multiplexer for transmitting the input signal or the output signal to the output side. 2. An output buffer for transmitting an output signal of an internal circuit arranged inside the semiconductor chip to an output pin of the semiconductor chip, and a reset terminal for receiving a system reset signal for executing initialization of the internal circuit. An input terminal to which an input signal of the internal circuit is input; a reset state is released by the input of the system reset signal, and the mode cyclically changes in response to a pulse signal input to the input terminal, and the reset state A state machine having a plurality of mode identifying terminals for outputting a mode identifying signal for identifying at least three modes including the first mode at the time when is released, and an input side of the internal circuit and the plurality of mode identifying terminals. One of the output buffers is connected to the input side of the output buffer, and the output side is connected to the input side of the output buffer. In response to the mode identification signal and the mode identification signal representing each of the two modes other than the first mode, the output signal, one of the logic levels output from one of the plurality of mode identification terminals, and A semiconductor integrated circuit, comprising: a multiplexer for transmitting a signal indicating the other to an output side.