JPS598009A - Microprocessor controller - Google Patents

Abstract

PURPOSE:To prevent an evil effect of undesired radiation, by stopping the operation of a clock generating circuit with use of a reset pulse generated from a microprocessor when the prescribed process is over. CONSTITUTION:When an input signal is applied to an input processing circuit 1, a clock generating circuit 3 starts its operation. Then a malfunction preventing circuit 6 is actuated, and a memory 7, an I/O, etc. can have executions. When a CPU4 finishes its processing, a program end signal is delivered. Then a reset pulse 11 is delivered from an output selection board 9 and then applied to a D-FF2. Thus the D-FF2 is reset, and the operation of the circuit 3 is stopped.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a microprocessor control device in a microprocessor-controlled instrument, etc., and the present invention eliminates the need for a clock by generating a lock required for the microprocessor only during the processing time of the microprocessor. This is intended to prevent radiation from becoming noise.

Training equipment that uses microconbeaters to control
For example, in a distortion measurement device that combines an oscillator and a distortion meter,
A microprocessor is used to set the frequency, level, etc. to predetermined values, and to set the distortion rate measurement state or the S/N measurement state.

In this case, the clock for the microprocessor becomes unnecessary radiation, which causes noise in the device under test (eg, radio, television, etc.).

For this reason, conventionally, as shown in FIGS. 1a and 1b, a printed circuit board A including a microprocessor (CPU) is housed in a shield case B, and external circuits such as external launches are
The connection was made through a through-type filter D.

However, as in the above conventional example, sold case B
The disadvantage of using this is that it is both expensive and heavy. Furthermore, since the filter D is inserted into the data line, etc., there are drawbacks such as slow data transmission.

The present invention eliminates the above-mentioned conventional drawbacks, and one embodiment of the present invention will be described below.

This embodiment is a distortion measurement device that combines an oscillator and a distortion meter, and is capable of setting frequencies and levels.

Distortion rate measurement, S/N measurement, etc. are controlled by a microconbeater.

In FIG. 2, 1 is an input processing circuit, and this input processing circuit 1 has frequency settings and level settings.

Input signals for S/N measurement and distortion rate measurement are input, and an input code is created based on this input signal, and a start pulse is created by a gate circuit in the input processing circuit 1. 2 is a D-type flip-flop (D-FF), and the start pulse output from the input processing circuit 1 is D-FF.
A mark is placed on the clock terminal (CK) of FF2, and the Q output changes from a low level to a high level at the timing of the rise of this start pulse. 3 is a clock generation circuit;
This clock generation circuit 3 operates to generate a clock when the Q output of the D-FF 2 becomes high level.

4 is a microprocessor (e.g. Intel 8085) (
The clock output from the clock generation circuit 3 is input to the CPU 4. 5 is a counter, and this counter 6 counts 81 clocks output from the clock generation circuit 3, and changes the output terminals 6a and 5b from a low level to a high level when a predetermined count is completed. The output of the output terminal 5a is sent to the reset terminal of the CPU 4. CPU4 (/i: Set when the output of output terminal 5a becomes high level. This is a 6-digit malfunction prevention circuit. This malfunction prevention circuit 6 is inserted in the control line 8 connecting the CPU 4, memory 7, and Ilo. When the output terminal 5b of the counter 5 becomes high level, a control signal outputted from the CPU 4 is applied to the memory 7, Ilo, etc. via the control line 8. That is, the clock generation circuit 3 starts operating and a predetermined number of clocks are output. When the clock of A1 is counted, the memory 7, work/○, etc. are put into the execution state.9 is an output selection port, and this output selection port 9 is outputted from the CPU 4 and sent through the one-way node 1o. The output selection board 9 outputs a reset pulse to the line 11 based on the program end signal from the CPU 4. This reset pulse is sent to the input processing circuit 1, D-
Applied to FF2. 12 is an address bus.

Next, the operation of this embodiment will be explained. In FIG. 2, when an input signal is applied to the input processing circuit 1, an input code corresponding to the input signal is set and a start pulse is generated. When a start pulse is applied to D-FF2, the Q output becomes high level and the blackout generation circuit 3
starts operating, and the clock is input to the CPU 4 and counter 6. When the counter 5 counts a predetermined number, the CPU 4 is set, the malfunction prevention circuit 6 operates, and the control signal output from the CPU 4 is input to the memory 7, Ilo, etc. via the control line 8. The memory 7, Ilo, etc. become executable.

The CPU 4 becomes executable through the following operations, and the process is thereafter executed according to the processing flow shown in FIG.

In FIG. 3, an initial check is performed in step 30, and then in step 31 the input code set in the input processing circuit 1 is taken into the CPU 4 via the data bus 1o. Next, in step 32, the input code is determined, and a level measurement process 33, a distortion rate measurement process 34, and a frequency setting process 35 are executed according to each input code. Step 36 is a step for determining whether frequency setting is to be performed continuously or continuously. When the above processing is completed, the processing result is latched in step 37. When this step 37 is completed, a program end signal is output from the CPU 4, a reset pulse is output from the output selection port 9 (step 38), this reset pulse is applied to the D-FF2, and the D-FF2 beam is set.
Clock generation circuit 3 stops.

In this way, in this embodiment, the oscillator used for distortion rate measurement,
Since the clock generation circuit 3 is only operated during the setting operation of the distortion meter, and the clock generation circuit 3 is not operated during actual distortion measurement, there is no clock noise. With this configuration, the clock is generated only when the microconbeater performs necessary processing, so the time during which unnecessary radiation occurs due to the clock can be shortened (approximately 10 msec in the case of the above embodiment). Three things that can easily prevent the negative effects of unnecessary radiation without using an expensive shield case.

[Brief explanation of the drawing]

1a and 1b are block diagrams and perspective views of a conventional microprocessor control device, FIG. 2 is a block diagram of a microprocessor control device according to an embodiment of the present invention, and FIG. 3 is a processing flow in the same device. It is a diagram. 1... Input processing circuit, 2... D-type flynog flop (G-FF), 3... Clock generation circuit, 4... Microprocessor (CPU )
, 5... Counter, 6... Malfunction prevention circuit, 7... Memory, 8... Control line, 9... Output selection port, 10...Data bus, 11...Line, 12...
address bus. Figure 3

Claims (1)

[Claims] means for generating a start pulse when an input signal is applied; a microprocessor for operating a clock generation circuit by the start pulse; a lock control means; and a microprocessor for executing predetermined processing in response to a clock output from the clock generation circuit. and means for generating a reset pulse based on a stop command output by the microprocessor when a predetermined process is completed, and applying the reset pulse to the clock control means to stop the clock generation circuit. A microprocessor control device characterized by: