JPS6284834U - - Google Patents

Info

Publication number
JPS6284834U
JPS6284834U JP17608785U JP17608785U JPS6284834U JP S6284834 U JPS6284834 U JP S6284834U JP 17608785 U JP17608785 U JP 17608785U JP 17608785 U JP17608785 U JP 17608785U JP S6284834 U JPS6284834 U JP S6284834U
Authority
JP
Japan
Prior art keywords
terminal device
printer
signal
transmission line
speed clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP17608785U
Other languages
Japanese (ja)
Other versions
JPH0418042Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1985176087U priority Critical patent/JPH0418042Y2/ja
Publication of JPS6284834U publication Critical patent/JPS6284834U/ja
Application granted granted Critical
Publication of JPH0418042Y2 publication Critical patent/JPH0418042Y2/ja
Expired legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図はこの考案のプリンタ制御回路の一実施
例を示すブロツク図、第２図はプリントモードに
おける各部の主要な動作波図、第３図は従来の画
像端末装置の説明図である。 図中、１０はＣＰＵ、１１はＲＯＭ、１２はＲ
ＡＭ、１３は入力キー装置、１４は図形文字発生
用のメモリ、１５はＣＲＴコントロール回路、１
６はプリンヨの入出力ポート、１７はゲート、２
０は表示装置、３０はプリンタ、３２はビデオＲ
ＡＭを示す。 FIG. 1 is a block diagram showing one embodiment of the printer control circuit of this invention, FIG. 2 is a diagram of main operating waves of each part in print mode, and FIG. 3 is an explanatory diagram of a conventional image terminal device. In the figure, 10 is CPU, 11 is ROM, 12 is R
AM, 13 is an input key device, 14 is a memory for generating graphic characters, 15 is a CRT control circuit, 1
6 is the input/output port of Purinyo, 17 is the gate, 2
0 is a display device, 30 is a printer, 32 is a video R
Indicates AM.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 各種の文字図形情報に対応して信号処理を行う
ことができる端末装置に伝送線を介して接続する
ようになされているプリンタにおいて、前記端末
装置から伝送線を介して供給されている映像信号
、同期信号及び高速クロツク信号を受領し、前記
映像信号を前記同期信号及び高速のクロツク信号
に同期してビデオＲＡＭに書き込み、所定の速度
で読み出してプリントアウトすることができるよ
うな回路をプリンタに設け；前記端末装置、又は
前記プリンタからのプリント指令があつたときは
、当該プリント指令が出力された時点から所定期
間だけ少なくとも前記高速クロツク信号を前記伝
送線に送出するようなゲート回路が前記端末装置
に設けられていることを特徴とするプリンタ制御
回路。 In a printer configured to be connected via a transmission line to a terminal device capable of signal processing corresponding to various character and graphic information, a video signal supplied from the terminal device via the transmission line; The printer is provided with a circuit that can receive a synchronization signal and a high-speed clock signal, write the video signal in a video RAM in synchronization with the synchronization signal and high-speed clock signal, read it out at a predetermined speed, and print it out. ; when a print command is received from the terminal device or the printer, the terminal device includes a gate circuit that transmits at least the high-speed clock signal to the transmission line for a predetermined period from the time when the print command is output; A printer control circuit characterized by being provided in.
JP1985176087U 1985-11-18 1985-11-18 Expired JPH0418042Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1985176087U JPH0418042Y2 (en) 1985-11-18 1985-11-18

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1985176087U JPH0418042Y2 (en) 1985-11-18 1985-11-18

Publications (2)

Publication Number Publication Date
JPS6284834U true JPS6284834U (en) 1987-05-30
JPH0418042Y2 JPH0418042Y2 (en) 1992-04-22

Family

ID=31116001

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1985176087U Expired JPH0418042Y2 (en) 1985-11-18 1985-11-18

Country Status (1)

Country Link
JP (1) JPH0418042Y2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63135143U (en) * 1987-02-24 1988-09-05

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5578390A (en) * 1978-12-07 1980-06-12 Nec Home Electronics Ltd Scanning speed conversion method for printer
JPS598009A (en) * 1982-07-06 1984-01-17 Matsushita Electric Ind Co Ltd Microprocessor controller

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5578390A (en) * 1978-12-07 1980-06-12 Nec Home Electronics Ltd Scanning speed conversion method for printer
JPS598009A (en) * 1982-07-06 1984-01-17 Matsushita Electric Ind Co Ltd Microprocessor controller

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63135143U (en) * 1987-02-24 1988-09-05

Also Published As

Publication number Publication date
JPH0418042Y2 (en) 1992-04-22

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