JPS596255U - Small computer with printer - Google Patents
Small computer with printerInfo
- Publication number
- JPS596255U JPS596255U JP9753382U JP9753382U JPS596255U JP S596255 U JPS596255 U JP S596255U JP 9753382 U JP9753382 U JP 9753382U JP 9753382 U JP9753382 U JP 9753382U JP S596255 U JPS596255 U JP S596255U
- Authority
- JP
- Japan
- Prior art keywords
- printer
- control circuit
- circuit
- numerical data
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Digital Computer Display Output (AREA)
- Calculators And Similar Devices (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
図面はこの考案の一実施例の回路図を示す。
１・・・・・・キーボード、３・・・・・・ＣＰＵ、
４・・・・・・バッファ、５・・・・・・印字制御回路
、６・・・・・・表示制御回路、７・・・・・・出力バ
ッファ、Ｇ１．Ｇ２・・・・・・ゲート回路。The drawing shows a circuit diagram of an embodiment of this invention. 1...Keyboard, 3...CPU,
4...Buffer, 5...Print control circuit, 6...Display control circuit, 7...Output buffer, G1. G2...Gate circuit.
Claims (1)
算機において、前記計算機の演算、印字、表示の各動作
を制御する制御回路と、この制御回路が出力する印字用
および表示用の数値データを記憶するバッファ回路と、
前記制御回路から印字開始信号が入力されると前記バッ
ファ回路に対し第１の読出しクロックを出力して該バッ
ファ回路内の前記数値データを読出し前記プリンタに送
出すると共にこの印字制御動作中ビジー信号を出力する
印字制御回路と、この印字制御回路が前記ビジー信号を
出力していない期間において前記バッファ回路に対し第
２の読出しクロックを出力して、 該バッファ回路内の
前記数値データを読出し前記表示装置に送出する表示制
御回路とを備えたことを特徴とするプリンタ付小型電子
計算機。In a small electronic computer with a printer that includes a printer as well as a display device, a control circuit that controls calculation, printing, and display operations of the computer, and a buffer that stores numerical data for printing and display output by this control circuit. circuit and
When a print start signal is input from the control circuit, a first read clock is output to the buffer circuit to read out the numerical data in the buffer circuit and send it to the printer, and a busy signal is output during this print control operation. a print control circuit to output, and a second read clock to the buffer circuit during a period when the print control circuit is not outputting the busy signal to read out the numerical data in the buffer circuit and read the numerical data to the display device. A small electronic computer with a printer, characterized in that it is equipped with a display control circuit that sends out data to the computer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9753382U JPS596255U (en) | 1982-06-30 | 1982-06-30 | Small computer with printer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9753382U JPS596255U (en) | 1982-06-30 | 1982-06-30 | Small computer with printer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS596255U true JPS596255U (en) | 1984-01-14 |
Family
ID=30231961
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9753382U Pending JPS596255U (en) | 1982-06-30 | 1982-06-30 | Small computer with printer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS596255U (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5279837A (en) * | 1975-12-26 | 1977-07-05 | Casio Comput Co Ltd | Device for information output control |
| JPS568039U (en) * | 1979-06-30 | 1981-01-23 |
-
1982
- 1982-06-30 JP JP9753382U patent/JPS596255U/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5279837A (en) * | 1975-12-26 | 1977-07-05 | Casio Comput Co Ltd | Device for information output control |
| JPS568039U (en) * | 1979-06-30 | 1981-01-23 |
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