JPS61124093U - - Google Patents

Info

Publication number
JPS61124093U
JPS61124093U JP776985U JP776985U JPS61124093U JP S61124093 U JPS61124093 U JP S61124093U JP 776985 U JP776985 U JP 776985U JP 776985 U JP776985 U JP 776985U JP S61124093 U JPS61124093 U JP S61124093U
Authority
JP
Japan
Prior art keywords
display data
register
parallel
time
serial
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP776985U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP776985U priority Critical patent/JPS61124093U/ja
Publication of JPS61124093U publication Critical patent/JPS61124093U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの考案の一実施例による表示回路図
、第2図はこの考案の一実施例による表示動作タ
イミング図、第3図は従来方式による表示回路図
、第4図は従来方式による表示動作タイミング図
である。 1…イメージメモリ、2…ゲート、3…レジス
タ、4…並―直列シフトレジスタ、5…CRT、
6…制御部。なお、図中同一符号は同一、又は相
当部分を示す。
Fig. 1 is a display circuit diagram according to an embodiment of this invention, Fig. 2 is a display operation timing diagram according to an embodiment of this invention, Fig. 3 is a display circuit diagram according to a conventional method, and Fig. 4 is a display according to a conventional method. It is an operation timing diagram. 1... Image memory, 2... Gate, 3... Register, 4... Parallel-serial shift register, 5... CRT,
6...Control unit. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 表示用データを格納するイメージメモリと、一
時その表示用データをラツチするレジスタと、そ
のレジスタ出力を時分割に制御する制御部と、時
分割された表示用データを並―直列変換する並―
直列シフトレジスタとを備えた表示データ制御回
路。
An image memory that stores display data, a register that temporarily latches the display data, a control unit that controls the register output in a time-sharing manner, and a parallel memory that converts the time-divided display data from parallel to serial.
A display data control circuit with a serial shift register.
JP776985U 1985-01-22 1985-01-22 Pending JPS61124093U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP776985U JPS61124093U (en) 1985-01-22 1985-01-22

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP776985U JPS61124093U (en) 1985-01-22 1985-01-22

Publications (1)

Publication Number Publication Date
JPS61124093U true JPS61124093U (en) 1986-08-05

Family

ID=30486428

Family Applications (1)

Application Number Title Priority Date Filing Date
JP776985U Pending JPS61124093U (en) 1985-01-22 1985-01-22

Country Status (1)

Country Link
JP (1) JPS61124093U (en)

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