KR800001585B1 - Automatic handling apparatus of electronic cash register - Google Patents

Abstract

An testing device of cash register checking the characteristics of each function within operating time of the function comprises of a circuits for time setting, -which is composed of a OR gate, timer(1)(100msec), counter(C+), memory circuit for time setting(MA), timer(2)(100msec, 1sec, 3sec 30sec)-memory circuit(MB) for appointing the connector and three decorders(DC1-DC3). The outputs(D1-D8) of the memory circuit(MB) is converted to the combined codes and connected with each taps(C1-C38) of decorder(DC1-DC3).

Description

Automatic operation device of cash register

1 is a block diagram of the present invention

2 is a time chart of the present invention.

3 shows the connector designation signal pulse selectivity of the present invention.

The present invention relates to an automatic operation apparatus for a cash register formed by forming a network in which time is specified and inspected for the inspection period of each function so as to automatically inspect the operation state of each function after assembling and producing the cash register. will be.

Conventionally, in order to inspect each function after assembling and manufacturing a cash register, it is necessary to manually operate the buttons of each function, which not only takes a lot of time for the test operation, but also has a troublesome operation. By using the reader method, all necessary standards and operation states to be inspected on the tape were memorized and tested by this method. However, in this test operation method, the pressing time of each button during the test operation is shorter than that of each function. Regardless of the length, there was a defect that it was not uniform and the unnecessary delay and the pushing time were long and it could not be an efficient inspection method under the mass production system.

The present invention is to store the test method and the test time of each function in the memory circuit in order to eliminate such defects in the prior art and to connect it to several memory circuits connected to a cash register to be tested through a connector (Connector) After pressing the start switch (Start SW), the timer circuit specified by the memorized inspection method is operated, supplying the proper time and automatically operating the cash register to quickly and accurately inspect all the functions. It will be described in detail as follows.

)에 인버어터(I)를 통하여 연결하고 콘넥터 지정용 기억회로(MB)의 집선택 단자(CS)에 연결한다.That is, the power supply (+ 5V) is connected to the input of the OR gate through the start switch, and the output terminal of the OR gate is connected to the counter circuit Ct through the timer 1 (100 m sec). 8 outputs (A _0- A ₇ ) of the counter circuit (Ct) are connected to the time-defining memory circuit (MA) and output (D) of this time-defining memory circuit (MA). ₁ -D _{4 is} connected to the timer circuit 2 (100m sec, 1Sec, 3Sec, 30Sec), and is configured to supply this output to the other input of the OR gate, and also to output the counter circuit Ct ( A ₀ -A _{7 is} supplied to the connector designating memory circuit (MB), and one end of the timer (1) (100m Sec) is the chip selector of the time designating memory circuit (MA) suitable for the inspection period. ) Terminals(

) Is connected to the selector terminal CS of the connector designating memory circuit MB.

In addition, the eight outputs (D _1- D ₈ ) of the memory for designating the connector (MB) are connected by the connectors (C ₁ -C ₃₈ ) through the decoder (DC ₁ ) (DC ₂ ) (DC ₃ ). It is a structure that is connected to a cash register.

)가 100m Sec 동안 ˝L˝(Low) 레벨이 유지되면서 동시에 카운터회로(Ct)의 입력(Cp)에 순차적인 클럭펄스가 공급되어서 카운터회로(Ct)의 출력펄스가 제2도의 (4)(5)(6)(7)(8)(9)(10)(11)과 같이 변화하는데, 이때 A₀-A₇펄스(4-11)는 A₀펄스(4)가 첫 번째 클럭 펄스의 다운(down)되는 순간 A₁펄스(5)가 업(up)되고, A₀펄스(4)의 두 번째 클럭펄스의 다운되는 순간 A₁펄스(5)가 다운되는 통상의 2진 카운터(Binary counter)와 같은 형식의 클럭상태로 표현되나 제2도에서는 지면상 A₃-A₇펄스(7-11)는 각기 하나의 선으로 표현되었으며, 이와 같이 변화하는 펄스에 의해서 시간지정용 기억회로(MA)가 동작하며 이 시간지정용 기억회로(MA)는 다음 검사해야할 기능의 시험기간을 타이머(2)에 의하여 지정하게 된다.The present invention of such a structure is first connected to the cash register assembled with the connectors (C ₁ -C ₃₈ ) and pressing the start switch (Start SW) by the timer (1) (100m Sec) as shown in FIG. The waveform is supplied to the chip select terminal CS of the counter circuit Ct and the connector designation memory circuit MB, and to the time designation memory circuit MA by the inverter I (2) of FIG. When the pulse signal is supplied, the chip select terminal of the memory

The low level is maintained for 100 m Sec while the sequential clock pulses are supplied to the input Cp of the counter circuit Ct, so that the output pulse of the counter circuit Ct is reduced to (4) ( 5) (6) (7) (8) (9) (10) (11), where A ₀ -A ₇ pulses (4-11) are A ₀ pulses (4) of the first clock pulse. down (down) time a ₁ pulse 5 that is up (up), a ₀ pulse (4) and the second down moment of the clock pulse a ₁ pulse (5) is down, the normal binary counter (binary that of In Figure 2, A _3- A ₇ pulses (7-11) on the ground are represented by a single line, and in this way, the time-defining memory circuit MA) is operated and this timed memory circuit MA specifies the test period of the next function to be checked by the timer 2.

That is, one of the timers of the timer circuit 2 (100m Sec, 3Sec, 30Sec) is designated by the pulses of (12) (13) 14 (15) of FIG. 2, and this pulse is the OR gate. After the level is set by the timer (1) (100m Sec) and continues the pulse for a predetermined time only when the time of 100m Sec by the timer (1) after the counter circuit (Ct) is sequentially changed by the output The timer 2 is operated by inputting one of the pulses 12, 13, 14 and 15 of FIG. The connector designating memory circuit MB is decoded by the output pulse of the counter circuit Ct, i.e., (4) (5) (6) (7) (8) (9) (10) (11) of FIG. The input pulses of (DC ₁ ) (DC ₂ ) and (DC ₃ ) are supplied to operate each connector C ₁ -C _38. At this time, the connector designation memory circuit MB is decoder DC ₁ ( DC ₂₎ (decode emitter ₍₁ DC) (DC ₂₎ pulse is a second degree (16, 17 for operating the (DC ₃₎₎ DC ₃₎ to specify a connector (C ₁ -C ₃₈₎ via the ( 18) (19) (20) (21) (22) (23) The decoder (DC ₁ ) (DC ₂ ) (DC ₃ ) is operated by the combination of eight pulse signals. Specifies.

As shown in FIG. 3, the first connector C ₁ has a pulse 16 of ˝H 펄스, pulse 17 of ˝L˝, pulse 18 of ˝L˝, and pulse 19 of ˝H ˝, pulse 20 is ˝L˝, pulse 21 is ˝L˝, pulse 22 is ˝H˝, and pulse 23 is ˝L˝, so that the designated signal number of connector C ₁ 10010010˝ and connector (C ₂ ) becomes “01111000˝. In this way, each connector (C ₁ -C ₃₈ ) is operated so that the cash register connected to the connector can be tested without any button operation. It was made possible.

That is, if it takes 33 seconds to settle any calculation, the time-defining memory circuit (MA) designates 33 seconds by specifying 3 seconds and 30 seconds each, and the connector designating memory circuit (MB) is the decoder (DC ₁ ). Designate each connector by pulse through (DC ₂ ) (DC ₃ ).

In this way, the time-defining memory circuit MA specifies a timer each time the input Cp of the counter circuit Ct increases by 1, and the connector-designating memory circuit MB also decodes the DC ₁ . ₂ ) (DC ₃ ) It is possible to designate the proper connector and to perform the operation test.

Claims (1)

As described above, the OR gate, the timer (1) (100 m Sec), the counter circuit (Ct), the time designation memory circuit (MA), and the timer circuit (2) (100 m Sec, 1Sec, 3Sec, 30Sec). ), The cash register's automatic control device comprising a time designating circuit and connecting it to three decoders DC ₁ , DC ₂ , and DC ₃ through the connector designating memory circuit MB. .

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