JPS55935A - Signal synchronization system - Google Patents

Signal synchronization system

Info

Publication number
JPS55935A
JPS55935A JP7376978A JP7376978A JPS55935A JP S55935 A JPS55935 A JP S55935A JP 7376978 A JP7376978 A JP 7376978A JP 7376978 A JP7376978 A JP 7376978A JP S55935 A JPS55935 A JP S55935A
Authority
JP
Japan
Prior art keywords
parity
cpu12
output
input
parity bit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7376978A
Other languages
Japanese (ja)
Other versions
JPS5747444B2 (en
Inventor
Takaharu Takai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP7376978A priority Critical patent/JPS55935A/en
Publication of JPS55935A publication Critical patent/JPS55935A/en
Publication of JPS5747444B2 publication Critical patent/JPS5747444B2/ja
Granted legal-status Critical Current

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  • Information Transfer Systems (AREA)

Abstract

PURPOSE: To read signals with high precision by reading unconditional request signals from remote input-output devices which operates asynchronously at the clock timing of a central processor in an electronic computer system.
CONSTITUTION: An unconditional request signal, set to output register 15 of input- output device 11 is given a parity bit by parity bit generator 16 and sent out via data common bus 13 to central processor (CPU)12, where when the result of the check by parity check circuit 17 is normal, it is fetched into control part 18. This read operation is performed at the clock timing of CPU12 and set signal S is sent from CPU12 to input-output device 11 via transmission line 19 to output the unconditonal request signal and also to give the parity bit; after the fixed time elapses, CPU12 makes a parity check, so that the control of parity will be excuted accurately.
COPYRIGHT: (C)1980,JPO&Japio
JP7376978A 1978-06-20 1978-06-20 Signal synchronization system Granted JPS55935A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7376978A JPS55935A (en) 1978-06-20 1978-06-20 Signal synchronization system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7376978A JPS55935A (en) 1978-06-20 1978-06-20 Signal synchronization system

Publications (2)

Publication Number Publication Date
JPS55935A true JPS55935A (en) 1980-01-07
JPS5747444B2 JPS5747444B2 (en) 1982-10-09

Family

ID=13527741

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7376978A Granted JPS55935A (en) 1978-06-20 1978-06-20 Signal synchronization system

Country Status (1)

Country Link
JP (1) JPS55935A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4760171A (en) * 1986-12-10 1988-07-26 Agency Of Industrial Science And Technology Process for producing ethanol

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4760171A (en) * 1986-12-10 1988-07-26 Agency Of Industrial Science And Technology Process for producing ethanol

Also Published As

Publication number Publication date
JPS5747444B2 (en) 1982-10-09

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