JPS5719828A - Data processing equipment - Google Patents

Data processing equipment

Info

Publication number
JPS5719828A
JPS5719828A JP9254480A JP9254480A JPS5719828A JP S5719828 A JPS5719828 A JP S5719828A JP 9254480 A JP9254480 A JP 9254480A JP 9254480 A JP9254480 A JP 9254480A JP S5719828 A JPS5719828 A JP S5719828A
Authority
JP
Japan
Prior art keywords
delay
cpu1
read
control signal
write
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9254480A
Other languages
Japanese (ja)
Inventor
Tomoji Nukiyama
Junichi Iwasaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP9254480A priority Critical patent/JPS5719828A/en
Publication of JPS5719828A publication Critical patent/JPS5719828A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microcomputers (AREA)
  • Information Transfer Systems (AREA)

Abstract

PURPOSE:To elevate the throghput of a system which has been provided with peripheral equipments whose data access time is different each other, by providing a terminal for receiving a delay request signal of a data access control signal, and a delay timing generating circuit, on a CPU ship. CONSTITUTION:When a time control signal C for requesting a delay of an access time is inputted to an input terminal 8 of a CPU1, in a data cycle by which read RD and write WR signals are outputted in the CPU1, a timing control signal generation part 3 is qualified by a time decided by a shift register 12, and it is possible to delay or extend read/write cycles. Its delay or extension timing is controlled by a synchronizing signal 11 in the CPU1, therefore, read/write processings are executed without providing a synchronizing circuit separately.
JP9254480A 1980-07-07 1980-07-07 Data processing equipment Pending JPS5719828A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9254480A JPS5719828A (en) 1980-07-07 1980-07-07 Data processing equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9254480A JPS5719828A (en) 1980-07-07 1980-07-07 Data processing equipment

Publications (1)

Publication Number Publication Date
JPS5719828A true JPS5719828A (en) 1982-02-02

Family

ID=14057320

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9254480A Pending JPS5719828A (en) 1980-07-07 1980-07-07 Data processing equipment

Country Status (1)

Country Link
JP (1) JPS5719828A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03111960A (en) * 1989-09-26 1991-05-13 Mitsubishi Electric Corp One-chip microcomputer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03111960A (en) * 1989-09-26 1991-05-13 Mitsubishi Electric Corp One-chip microcomputer

Similar Documents

Publication Publication Date Title
AU510240B2 (en) Common polling logic for input/output interrupt or cycle steal data transfer requests
JPS5450329A (en) Copier control device using plural micro-computers
ES473022A1 (en) Arrangement for micro instruction control
JPS5719828A (en) Data processing equipment
AU6672681A (en) Data transmission
JPS55121521A (en) Data bus control system
JPS5483726A (en) Memory access processing system of data processing system
JPS5587220A (en) Interface controller
SE7710847L (en) DEVICE FOR GENERATING FOR A SELECTED ANALOG SIGNAL EXCELLENT DIGITAL DATA
JPS52129241A (en) Memory control system
GB2016757A (en) Display Terminal
JPS5374856A (en) Data process system
JPS5757369A (en) Access control system
JPS5457918A (en) Memory access processing system
JPS51117845A (en) Electronic computer fault diagnostic equipment
JPS56168256A (en) Data processor
JPS5622157A (en) Process system multiplexing system
ES8103407A1 (en) Data processing system
JPS55121541A (en) Arithmetic unit
JPS5214323A (en) Shift register data transfer control system
JPS55935A (en) Signal synchronization system
JPS5654559A (en) Memory unit
JPS57105056A (en) Register control system
JPS55140972A (en) Coordinate value checking circuit
JPS6473876A (en) Moving image processor