JPH0458335A - Trouble reporting circuit - Google Patents

Abstract

PURPOSE:To facilitate the analysis of an area where a true trouble occurs by providing a suppression inhibiting means which prevents plural trouble detection means from setting the trouble detection signals to a corresponding trouble flag means and a means which supplies the trouble detection signal sent from the corresponding trouble flag means to this means with bypass while the suppression is inhibited for setting the trouble detection signal. CONSTITUTION:A suppression inhibiting flag means 11 decides whether the trouble detection signals of the trouble detection means (circuits) 1 - 3 should be set to the corresponding trouble flag means (circuits) 7 - 9 or not. Then the bypass means (circuits)12 - 14 supply the trouble detection signals of the circuits 1 - 3 to the circuits 7 - 9 respectively with bypass when the suppression is inhibited for the trouble detection signals. Thus the suppression circuits 4 - 6 are set in the suppression states when the circuit 1 detects a trouble. However the subsequent trouble detection signals of the circuits 2 and 3 can be set to the circuits 8 and 9 respectively since the circuits 13 and 14 supply the trouble detection signals to the circuits 8 and 8 with bypass. Thus it is possible to detect the logical designing errors and the hardware troubles.

Description

TECHNICAL FIELD The present invention relates to a failure reporting circuit, and more particularly to a failure reporting circuit for reporting a detected hardware failure in a data processing device to a failure diagnosis device.

Prior Art A block diagram of a conventional failure reporting circuit of this type is shown in FIG. For example, three failure detection circuit units 22.3 are provided, and each of these failure detection signals 101 to 103 is sent to the corresponding failure flag circuit 70, 80 through the corresponding suppression circuit 40, 50, 60, respectively. 90 respectively.

These fault flag circuits set corresponding fault detection signals, and the set output of each flag is sent to the OR circuit 10.
The signal is outputted as a report signal 104 to a fault diagnosis circuit (not shown) via the circuit. This signal 104 is simultaneously transmitted to the suppression circuits 40 and 5
0.60, and each failure detection signal is inhibited from being set in the corresponding failure flag circuit 70.8090 thereafter.

FIG. 13 is a circuit diagram showing an example of the suppression circuit 40, which is composed of an AND gate 42 that generates an inverted signal of the failure report signal 104 by the inverter 41 and the failure detection signal 101.

Therefore, when the report signal 104 is "0", this circuit 40
When a failure is not reported), the failure detection signal 101 is output as is to the failure flag circuit 70, and when it is "1" (when a failure is reported), the failure detection signal 101 is inhibited. The other suppression circuits 5060 also have the same configuration.

FIG. 14 is a circuit diagram showing a specific example of the failure flag circuit 70, in which the failure flag F/P 72, the output of this F/F 72, and the output of the suppression circuit 40 are operated by two people.
1, and the output of this OR gate 71 causes F/F
72 sets are made.

Therefore, when the output of the suppression circuit 40 is "1" (indicating a failure), "1" is set in the F/F 72, and it remains set until it is reset or sorted by a scan operation, etc., and the failure flag is set. It turns out.

Other failure flag circuits 80 and 90 have the same configuration.

In the configuration of FIG. 12, the failure flag circuit 7080.9
Each F/F 72 of 0 is set to "0" by the scan mode when the device is started up, and is in a state where no failure has occurred. Therefore, the output of the OR circuit 10 becomes "0", and each AND gate 42 of the suppression circuit 40°50.60
are all open.

In this state, when the detection circuit 1 detects a failure, the failure detection signal 101 becomes "1" and is supplied to the failure flag circuit 70 via the suppression circuit 40. Therefore, F/P
72 is set to "1" and at the same time, the output of the OR circuit 10 becomes "1" and a failure report is made.

Since the report signal 104 of "1" is inputted to the inhibition circuit 40.5060, each AND gate 42 responds to this.
are all closed, and subsequent failure detection signals 101, 10
2. LO3 is all suppressed and is not supplied to the failure flag circuit. This is a necessary function to identify the part that has failed in the first place.

Recently, due to the increasing complexity of processing in one clock cycle due to the increase in the processing speed of elements, and the increase in the capacity of logic installed in one module due to miniaturization of elements, the number of logic stages has increased. Errors are more likely to occur.

For this reason, in the structure shown in Figure 12, if a corresponding F/F is set to "1" due to a pseudo fault caused by a logic design error, then other faults may occur due to a true fault or other logic design error. This method has disadvantages in that the F/F is not set, making it difficult to analyze the problematic part, and the analysis process takes time.

OBJECTS OF THE INVENTION An object of the present invention is to provide a failure reporting circuit that facilitates analysis of other true failure locations even when a pseudo failure occurs.

Structure of the Invention According to the present invention, a plurality of fault detection means, a plurality of fault flag means provided corresponding to each of these fault detection means and for setting a fault detection signal of the corresponding fault detection means, and a plurality of fault flag means for setting a fault detection signal of the corresponding fault detection means, OR means for generating a fault signal when at least one of the outputs is set, and an OR means provided corresponding to the fault detection means, and a corresponding fault detection means in response to generation of the fault signal from the OR means. a plurality of inhibiting means for inhibiting setting of a failure detection signal in a corresponding failure flag means, the failure detection circuit inhibiting the setting of a failure detection signal by the failure detection means in a corresponding failure flag means; a deterrent prohibition means for instructing whether or not the occurrence of a malfunction occurs; and a deterrent prohibition means provided corresponding to the failure detection circuit, and when the deterrence is prohibited by the deterrence prohibition means, a failure detection signal from the corresponding failure detection means is sent to the corresponding failure flag means. A failure reporting circuit characterized in that it includes a plurality of bypass means each bypassing and supplying the power.

Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of a first embodiment of the present invention, and parts equivalent to those in FIG. 12 are designated by the same reference numerals. In this example, the failure detection circuits 1 to 3 are different from the conventional configuration shown in FIG.
Bypass circuits 12 to 14 respectively corresponding to the bypass circuits 12 to 14 and failure detection signals 101 to 101 to 14 corresponding to the bypass circuits 12 to 14, respectively.
Suppression prohibition flag that indicates the presence or absence of bypass of 103]1
This is the addition of

The inhibition prohibition flag 11 is a flag that can be set or reset only by a scan operation, and when set to "1", outputs a inhibition inhibition signal to each of the bypass circuits 12 to 14.

In response to this inhibition prohibition signal, each bypass circuit 12-14 bypasses the corresponding failure detection signal 101-103 and supplies it to the corresponding failure flag circuit 7-9, respectively. The failure flag circuit 7 has the configuration shown in FIG.
It has a human-powered or gate 73, and this or gate 73
The P/F 72 is set by the output. The other failure flag circuits 8.9 also have the same configuration.

Here, if the suppression prohibition flag 11 is set to "0", each bypass circuit 12 to circuit 4 all output "0", and therefore, in this case, the operation is the same as the conventional example shown in FIG. I do.

On the other hand, when the inhibition prohibition flag 11 is set to "1",
Since the inhibition prohibition signal of "]" will be output to each bypass circuit 12 to 14, each bypass circuit 12 to
14 operates to bypass the corresponding failure detection signals 101 to 103 to the corresponding failure flag circuit.

The operation shown in FIG. 1 in this state will be described. When the device is started up, all F/Fs 72 of the failure flag circuits 7 to 9 are set to "0" by a scan operation, and the inhibition prohibition flag 1 is set.
1 is set to "1".

Therefore, the suppression circuits 4 to 6 receive the corresponding failure detection signals 101 to 1.
03 to the corresponding failure flag circuits 7-9, respectively. At this time, if the detection circuit 1 detects a failure, the failure detection signal 1
01 becomes "1".

Therefore, “1” is set in the F/F 72 of the corresponding failure flag circuit 71.
is set, and in response, the OR circuit 10 reports the failure report signal 104 as "1". At the same time, the signal 104 being "1" closes the AND gates 42 (see FIG. 13) of each of the suppression d-circuits 4 to 6, resulting in a suppression state.

However, each of the bypass circuits 13 and 14 receives corresponding failure detection signals 102 and 1 due to the suppression prohibition flag 11 being "1".
03 is bypassed and supplied to the corresponding failure flag circuits 8 and 9, respectively, so that the other failure detection circuits 2 and 3
The subsequent failure detection signal is sent to the corresponding failure flag circuits 8 and 9.
Therefore, it becomes possible to set each of them.

Therefore, by scanning and reading out the contents of these failure flag circuits 7 to 9, it becomes possible to analyze the failure location.

FIG. 3 is a block diagram showing a second embodiment of the present invention, and parts equivalent to those in FIG. 12 and FIG. 1 are designated by the same reference numerals. To explain the different parts from Figure 1,
Failure report inhibition flag 1 instead of inhibition inhibition flag 11 in the figure
5 is provided, and by this flag output, the bypass circuits 12 to 1 are
4 is controlled.

Furthermore, the report signal 104 of the OR circuit 10 is led to a fault diagnosis circuit (not shown) via the fault report suppression circuit 16, and whether or not this fault report is allowed is controlled by a fault report suppression flag 15.

Therefore, as shown in the figure, the failure report suppression circuit 16 connects the inverter 1 which manually outputs the flag output of the failure report suppression flag 15.
61, and an ant gate 162 that handles the inverter output and the failure report signal 104 by two people.

The failure report suppression flag 15 is a flag that can be set and reset only by a scan operation, and when it is “1”, it issues a failure report suppression instruction to the failure diagnosis circuit 16 and also sends a corresponding failure detection signal to the bypass circuits 12 to 14. 101～
103 is a bypass instruction.

If the failure report suppression flag 15 is "0", the bypass circuits 12 to 14 are all outputting "0" as in the case of FIG. 1, and therefore, this case is the same as the conventional example of FIG. At this time, since the failure report suppression circuit 16 does not suppress the failure report signal 104, this signal 104
will be directly derived to the fault diagnosis circuit.

The case where the failure report suppression flag 15 is "]" will be described. In this case, since the gate 162 of the failure report suppression circuit 16 is in a closed state, the failure report signal 104 of the OR circuit 10 is not reported and is suppressed. This is useful for not reporting a pseudo-failure to the fault diagnosis circuit when, for example, circuit 7 of the fault flag circuits is set due to a logical design error or the like.

In response to the setting of this failure flag circuit 7, the OR circuit 10
A report signal 104 is output from 10, and this signal 104 causes each suppression circuit 4 to 6 to output the corresponding failure detection signal 101 to 10.
Deter 3. However, the failure report suppression flag 15 is “1”.
'', the bypass circuit 5.6 is in the bypass state, and therefore the failure detection signal 10 due to the next real failure occurs.
2.103 and supplies it to the corresponding failure flag circuits 8 and 9.

Therefore, at this time as well, it is sufficient to scan out the contents of the failure flag circuits 7 to 9.

FIG. 4 is a block diagram showing a third embodiment of the present invention, and parts equivalent to those in the previous figures are designated by the same reference numerals. In this example, in contrast to the conventional example shown in FIG. 12, a failure report suppression flag 15 is used, and depending on the state of this flag 15, the failure report signal 104 which is the output of the OR circuit 10 is suppressed from being reported to the failure diagnosis circuit. Failure report suppression circuit 16 that controls
It has been established that The inhibition of each of the inhibition circuits 4 to 6 is controlled by the report output of this circuit 16.

When the failure report suppression flag 15 is set to "0," the failure report suppression circuit 16 derives the failure report signal 104 from the OR circuit 10 as it is and reports it to the failure diagnosis circuit, similar to the example shown in FIG. .

Therefore, at this time, for example, the failure detection signal 1 from the detection circuit 1
When 01 is output, "1" is set in the failure flag circuit 70 via the inhibition circuit 4. Therefore, a failure report of "1" is derived via the OR circuit 10 and the failure report suppression circuit 16.

At the same time, the suppression circuits 4 to 6 enter the suppression state and do not supply the subsequent generation of failure detection signals 101 to 103 to the corresponding failure flag circuits 70, 80, and 90, and the operation is the same as that of the conventional configuration.

However, when the failure report suppression flag 15 is set to "1," failure reporting is suppressed by the failure report suppression circuit]6. Therefore, it is effective when a pseudo failure occurs due to a logic design error or the like.

At this time, since the inhibition circuits 4 to 6 do not enter the inhibition state, the failure detection signals io1 to 103 are supplied to the corresponding failure flag circuits 70, 80, and 90, respectively, and can be set, so that the failure location can be analyzed. Failure flag circuit 70, 80
．． 90 scan outs makes it easier.

FIG. 5 is a block diagram showing a fourth embodiment of the present invention, and parts equivalent to those in the previous figures are designated by the same reference numerals. In this example, the failure report suppression circuit 16 in the example of FIG.
are provided corresponding to each failure flag circuit 70, 80.90, respectively, and whether or not the flag output of the corresponding failure flag circuit 70, 80.90 is derived to the OR circuit 10 by these report suppression circuits 16A, 16B, 16C. is controlled.

The output 104 of the OR circuit 10 causes each suppression circuit 4 to
It is the same as the example shown in FIG. 1 that the inhibition control steps .about.6 are performed.

When the failure report suppression flag 15 is "0", each of the report suppression circuits 16A, 16B, and 16C is not in a suppressed state, and therefore is similar to the conventional example shown in FIG.

If it is "1", it is in the inhibited state, so no failure is reported to the fault diagnosis circuit, and at the same time each of the inhibiting circuits 4 to 6 does not enter the inhibited state. Therefore, it has the same effect as the embodiment shown in FIG.

FIG. 6 is a block diagram showing a fifth embodiment of the present invention, and parts equivalent to those in the previous figures are designated by the same reference numerals. In this example, each suppression circuit 18 is different from the conventional example shown in FIG.
A fault suppression instruction circuit 17 is added for instructing which circuit of 20 to 20 is to be inhibited.

FIG. 7 is a diagram showing a specific example of the fault suppression instruction circuit]7, in which a register 700 is a register indicating which fault detection of fault detection circuits 1 to 3 is to be suppressed, and the register 700 is a register that indicates which fault detection is to be suppressed in the fault detection circuits 1 to 3. The detection circuit number is set by scan-in when starting up the device.

Decoder 701 decodes the contents of register 700 and outputs suppression signals 110 to 112 to detection suppression circuits 18 to 20 corresponding to the detection circuits.

FIG. 8 is a diagram showing the relationship between the contents of register 700 and output lines 110 to 112 of decoder 701.

When these output lines are "0", it is not inhibited, and when these output lines are "1", it is inhibited.

An example of each inhibit circuit 18 is shown in FIG. 9, and the other circuits 19 and 20 have the same configuration. Output 1 of decoder 701
10 is a human-powered inverter 181 and a report signal 104
The inverter 182 which uses human power, and the inverter 1
It consists of an AND gate 183 which handles each output of 81 and 182 and a failure detection signal 101 by three people.

When the value "0" is set in the register 700 of the failure suppression instruction circuit 17, all outputs 110 to 1 of the decoder 701
112 are all “0”, so all the inhibit circuits 18
~20 are in a non-inhibited state. Therefore, in this case, the same operation as the conventional example shown in FIG. 12 is performed.

When the value "]-" is set in the register 700,
Only the output 110 of the decoder 701 becomes "1", so only the inhibiting circuit 8 becomes inhibited, and the other circuits 19.
20 becomes a non-inhibited state.

Therefore, the failure detection signal 1.01 from the detection circuit 1 is suppressed by the suppression circuit 18 and is not supplied to the failure flag circuit 70. Therefore, in this case, it is effective when it is known in advance that there is a logic design error and the detection circuit 1 will detect a pseudo fault.

The same holds true for the inhibition of the other inhibition circuits 19 and 20.

Incidentally, also in the fourth embodiment of the present invention shown in FIG.
The failure report suppression flag 15 has the same configuration as the failure suppression instruction circuit 17 shown in FIG. 6, and each decoder output 11.0
-112 to the report suppression circuit]-6A16B and 16C, the same effect as the fifth embodiment of FIG. 6 will be produced.

FIG. 10 is a diagram showing an application example in which the failure reporting circuits of the first to fifth embodiments described above are applied systematically. The failure reporting circuit 26 is constructed as shown in FIG. This FIG. 11 has the same configuration as the conventional example in FIG. 12, and the failure reporting circuits 21 to 2B (24, 25) according to the present invention are used in place of the failure detection circuits 1 to 3 in FIG. ing.

Even when the fault reporting circuit 21 detects a pseudo fault, the fault reporting circuit 21 can always suppress its output.

Therefore, the failure reported by the failure reporting circuit 22.23 can be reported to the failure diagnosis circuit via the failure reporting circuit 26.28.

Effects of the Invention As described above, according to the present invention, even if a pseudo-fault occurs in logic design, the true fault detected by another fault detection circuit is set in the fault flag, so that the functionality of the device is improved. If this fault flag is read out by scan-out or the like at the end of a test or the like, it is effective to discover errors in logic design or hardware faults.

In addition, in the second to fourth embodiments, in addition to the effect of the first embodiment, it is possible to suppress the reporting of pseudo-faults, so when the fault reporting circuit is configured hierarchically as shown in FIG. This has the effect of making it possible to report the failure of other true failure reporting circuits.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a first embodiment of the present invention, FIG. 2 is a diagram showing a specific example of the failure flag circuit 7 of FIG. 1, and FIGS.
6 is a block diagram of the second to fifth embodiments of the present invention, FIG. 7 is a diagram showing a specific example of the failure prevention instruction circuit 17 in FIG. 6, and FIG. 8 is a decoder in the failure prevention instruction circuit 17. 70
FIG. 9 is a diagram showing the input/output relationship of FIG. 1, and FIG.
8, FIG. 10 and FIG. 11 are system configuration diagrams showing application examples of the present invention, FIG. 12 is a block diagram of a conventional failure reporting circuit, and FIG. 13 is the suppression circuit of FIG. 12. 4
FIG. 14 is a diagram showing a specific example of the failure flag circuit 70 of FIG. 12. Explanation of symbols of main parts 1-3...Failure detection circuit 4-6゜7-9 18-20 70.80.90...Fault flag circuit 40.5
0.60...Suppression circuit 10...OR circuit 11...Suppression prohibition flag 12-14...Bypass circuit 15...Failure report Inhibition flag 16...Failure report suppression circuit 17...Failure suppression instruction circuit

Claims (5)

[Claims] (1) A plurality of fault detection means, a plurality of fault flag means provided corresponding to each of these fault detection means and for setting a fault detection signal of the corresponding fault detection means, and at least one of the outputs of these fault flag means. OR means for generating a failure signal when set, and the failure detection means provided respectively in correspondence with the failure detection signal from the corresponding failure detection means in response to generation of the failure signal from the OR means. A failure detection circuit including a plurality of inhibiting means for inhibiting setting of a failure flag in a corresponding failure flag, the circuit for instructing whether or not to inhibit setting of a failure detection signal by the failure detection means in a corresponding failure flag. A deterrence inhibiting means is provided correspondingly to the failure detecting circuit, and when inhibition is prohibited by the inhibiting inhibiting means, a failure detection signal from the corresponding failure detecting means is bypassed and supplied to the corresponding failure flag means, respectively. A failure reporting circuit comprising a plurality of bypass means. (2) A plurality of fault detection means, a plurality of fault flag means provided corresponding to each of these fault detection means and for setting a fault detection signal of the corresponding fault detection means, and at least one of the outputs of these fault flag means. OR means for generating a failure signal when set, and the failure detection means provided respectively in correspondence with the failure detection signal from the corresponding failure detection means in response to generation of the failure signal from the OR means. A failure detection circuit including a plurality of inhibiting means for inhibiting setting of a failure flag in a failure flag means, a failure report inhibiting instruction means for instructing whether or not to suppress a failure report, and a failure report inhibiting instruction means for instructing whether or not to suppress a failure report; a reporting means for leading the output of the OR means to the outside as a failure report signal in response to the failure report, and a reporting means provided corresponding to the failure detection circuit, and a corresponding failure detection means when the failure report is inhibited by the failure report inhibition instruction means. a plurality of bypass means for bypassing and supplying a failure detection signal to a corresponding failure flag means, respectively. (3) A plurality of fault detection means, a plurality of fault flag means provided corresponding to each of these fault detection means and for setting a fault detection signal of the corresponding fault detection means, and at least one of the outputs of these fault flag means. an OR means for generating a failure signal when set; a failure report suppression instruction means for instructing whether to suppress a failure report; A corresponding failure flag of a failure detection signal from the failure detection means is provided corresponding to a reporting means for outputting a report signal to the outside and the failure detection means, and in response to generation of a failure report from the reporting means. A failure reporting circuit comprising: a plurality of inhibiting means for inhibiting setting to the means. (4) A plurality of fault detection means, a plurality of fault flag means provided corresponding to each of these fault detection means and for setting a fault detection signal of the corresponding fault detection means, and an instruction as to whether or not to suppress a fault report. A plurality of report suppressing means are provided corresponding to the failure report suppression instructing means and the failure flag means, respectively, and suppress and control the outputs of the corresponding failure flag means in accordance with the instructions of the failure report suppressing instructing means, and these report suppressing means. OR means for generating a fault signal when at least one of the outputs of the means indicates a fault; and corresponding fault detection means provided corresponding to the fault detection means in response to generation of the fault signal from the OR means. A failure reporting circuit comprising a plurality of inhibiting means for inhibiting setting of a failure detection signal from the means to a corresponding failure flag means. (5) A plurality of failure detection means, a plurality of failure flag means provided corresponding to each of these failure detection means and for setting a failure detection signal of the corresponding failure detection means, and at least one of the outputs of these failure flag means. OR means for generating a failure signal when set, and the failure detection means provided respectively in correspondence with the failure detection signal from the corresponding failure detection means in response to generation of the failure signal from the OR means. A failure detection circuit comprising a plurality of inhibiting means for inhibiting setting of a failure flag in a failure flag means, characterized in that it includes inhibiting instruction means for constantly issuing an inhibiting instruction to a specific inhibiting means among the inhibiting means. Fault detection circuit.