JPH01192161A - Semiconductor device - Google Patents

Abstract

PURPOSE:To divide a circuit into sections in preparation for a troubleshooting diagnostic test by a method wherein shift registers connected in series to each other are inserted between arbitrarily designated functional blocks also connected to each other, a test input terminal is connected to the shift registers, and a test control circuit capable of controlling the test input terminal and shift registers is provided. CONSTITUTION:Signals inputted at an input terminal group 10 are supplied to shift registers 17 through functional blocks 12 (A, B, and C), respectively. During routine operations the shift registers 17 work in a through mode, outputting to a functional block D the signals from the functional blocks A, B, and C, in parallel as received. When a trouble is to be detected in an examination or diagnosis, the shift registers 17 operate in a test mode. A signal at a test control terminal 16 throws the shift registers 17 into a shift register mode, when the shift registers 17 store signals outputted by the functional blocks A, B, and C. The signals stored in the shift registers 17 travel through the group of the shift registers 17, to be outputted at a test output terminal 15 bit by bit in series.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device that facilitates testing and diagnosis in logic error analysis during semiconductor device design and development and failure analysis after design and development.

[Conventional technology]

Conventionally, failure testing and diagnosis of this type of semiconductor device involves applying a plurality of so-called test patterns to the input terminal, in which a desired output value is checked at the expected output terminal of a logic circuit when a specified input value is applied to the input terminal. Fault tests and diagnosis were performed by comparing the output value at the time of failure with the expected output value.

FIG. 3 is a block diagram for explaining, as an example, a conventional technique of a semiconductor device composed of four functional blocks. Here, a functional block is one when a semiconductor device is divided.
One unit. In the conventional method, it is difficult to identify a fault diagnosis by testing and diagnosing a semiconductor device consisting of a plurality of functional blocks 32 as shown in FIG. ! i
The upper and lower stages of the functional blocks connected in series, the third
In the figure, it is difficult to isolate failures between functional blocks A, B, and C and functional block D, so it was necessary to input many test patterns. In addition, the scan path method (Correia, M., “Introductory
onto a LSI Te5t System,”
14th f)sign AutomationCo
nference Proceedings, pp.
, 460-461 + Jun.

(1977) required an increase in circuitry by 10-20% of the total.

[Problem that the invention seeks to solve]

In the conventional fault detection technology using testing and diagnosis described above,
There are drawbacks such as an increase in failure test time, an increase in test pattern creation time, or an increase in circuits due to an increase in the number of test patterns.

In contrast to the conventional semiconductor device described above, the present invention enables the output of each functional circuit in the semiconductor device to be observed from the test output terminal, and the input of each functional circuit to be input from the test input terminal. have differences.

[Means for solving problems]

The semiconductor device of the present invention includes shift registers connected in series between arbitrary functional blocks connected to each other, a test input terminal and a test output terminal connected to the shift registers, and the shift registers. Equipped with a test control circuit for control.

〔Example〕

Next, one embodiment of the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention. In the prior art, the signal lines inputted from the input terminal group 10 are connected to the function block D as shown in FIG. Each is input to the register 17. The shift register 17 operates in a through mode in normal operation, and outputs the signals of the functional blocks A, B, and C in parallel to the functional block D as they are. Operates in test mode when detecting failures through testing and diagnosis.
The shift register 17 is switched to the shift register mode from the test control terminal 16, and the signal outputs of the functional blocks A, B, and C are held in the shift register 17. The held signal passes through a series-connected shift register group 17 and is serially output one bit at a time to the test output terminal 15. That is, the outputs of the functional blocks A, B, and C can be output to the test terminal 15.

On the other hand, for testing and diagnosis of functional block D, a test pattern that targets only functional block D is serially input to the test input terminal 14, and the test pattern is set in the shift register 17 selected in shift register mode. Accordingly, an output can be obtained from the output terminal group 13 regardless of the states of the functional blocks A, B, and C.

As described above, by comparing the output values of the test output terminal 15 and the output terminal group 13 with the expected output values, it is possible to test and diagnose the correctness of each functional block.

FIG. 2 is a block diagram showing a second embodiment of the invention. The test diagnosis of functional blocks A, B, C, and D is the same as that described in the embodiment shown in FIG. However, the output of the functional block D is output from the test output terminal 25 via the shift register 27 instead of the output terminal group 23. For the test diagnosis of the function block E, a predetermined test pattern for failure detection for the function block E is inputted from the test input terminal 24, and is set as an input to the function block E via the shift register 27, and the expected output value is set. The test can be performed by diagnosing using the output terminal group 23.

〔Effect of the invention〕

As explained above, the present invention provides a test input/output terminal between logic blocks and a control circuit that enables input/output of the logic block from the test input/output terminal. At the time of detection, it is possible to divide the circuit for test diagnosis, making it easier to create test patterns, reducing test time, and allowing test diagnosis to be performed in detail.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a first embodiment of the present invention;
The figure is a plot diagram showing a second embodiment of the present invention, and FIG. 3 is a block diagram showing a conventional embodiment. 10... Input terminal group, 11... Signal line group, 12... Functional blocks A, B, C, D, 1
3...Output terminal group, 14...Test input terminal, 15...Test output terminal, 16...
...Test control terminal, 17...Shift register, 20...Input terminal group, 21...Signal line group, 22...Function block A ,B,C,D
. El 23... Output terminal group, 24...
Test input terminal, 25...Test output terminal, 2
6... Test control terminal, 27... Shift register, 30... Input terminal group, 31...
...Signal line group, 32...Functional blocks A, B
, C, D, 33...Output terminal group. Agent Patent Attorney Shinsuke Uchihara■ 3rd WJ

Claims (1)

[Claims] In a semiconductor device composed of a plurality of functional blocks, the output of at least one of the functional blocks is received as an input signal, the control signal operates in a through mode in normal operation, and the input signal is output to the next functional block. , when a failure is detected, it operates as a test mode,
A semiconductor device comprising a shift register that serially outputs the input signal to the outside, serially receives the test input signal, and inputs the test input signal in parallel to the next functional block.