JPH04273078A - Method of failure detection - Google Patents

Abstract

PURPOSE:To detect a faulty tip in a multi-tip package by using a scan pass. CONSTITUTION:Registers 31a and 32a are mutually connected by a scan pass, and registers 31b and 32b on the final stage are used to set an identification code consisting of plural bits for failure detection. A mode register 3 holds a condition for setting the identification code by a mode setting signal 'a' to be set at a maintenance diagnosis mode. An identification code writing means 4 writes the identification code in the registers 31b and 32b through a writing data line 4a in a mode signal 'b'. It is thus possible to detect a faulty tip easily without need for a large-scale hardware.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the detection of a faulty chip in a multi-chip package including a plurality of LSI chips, and more particularly to a fault detection method using a scan path.

0002

2. Description of the Related Art Conventionally, a scan path has been used as a method for detecting failed chips in a multi-chip package (hereinafter referred to as MCP) which is configured by mounting a plurality of LSI chips. Data is input from the scan-in side of the MCP, and serial data having a prescribed pattern is output to the shift-out side after passing through the flip-flops of all LSI chips in the MCP. In the scan path method, by checking this and confirming the validity of the serial out data, it is possible to confirm the normality of the chip.

0003

[Problems to be Solved by the Invention] In the above-mentioned conventional fault detection method using a scan path, a fault is determined based on whether scan-in data is scanned out normally. Detectable.

However, it has been difficult to determine which chip inside the MCP has failed. In the conventional method, in order to actually detect failures on a chip-by-chip basis,
It is necessary to remove the detected defective MCP from the device and then test it. That is, there is a drawback that a defective chip cannot be detected unless it is confirmed using a dedicated tester or the like.

SUMMARY OF THE INVENTION An object of the present invention is to provide a failure detection method that eliminates the above drawbacks and is configured to easily detect which LSI chip has failed.

[0006]

[Means for Solving the Problems] The present invention is a failure detection method for a multi-chip package in which a plurality of LSI chips each including a group of flip-flops are mounted and the groups of flip-flops are cascaded by a scan path. a mode register that can be set to a maintenance diagnosis mode when a maintenance diagnosis mode occurs; a data writing means for storing an identification code indicating a value specified when setting the maintenance diagnosis mode in the mode register in the final stage of the flip-flop group; and a scan clock signal. and connecting means for sending the identification code as scan-in data for the next stage upon application of the identification code.

[0007]

Embodiments Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram schematically showing an embodiment of the present invention.

FIG. 3 is a perspective view showing the appearance of FIG. 1. 1 and 3, 1 is an MCP, and a plurality of L
SI chips 21 to 2C are mounted. These LSI chips 21 to 2C are cascade-connected by a scan path 2, and the scan-in data input from the scan-in terminal of the MCP 1 is shifted by applying a scan clock signal, and transferred from the LSI chip 21 to the LSI The signal is sequentially propagated to the chip 22 and up to the LSI chip 2C, and is output from the scan-out terminal.

FIG. 2 is an explanatory diagram regarding the scan path shown in FIG. 1. In FIG. 2, 31 and 32 are arbitrary two LSI chips that are consecutive on the scan path connection within the MCP 1, respectively. 31a and 32a are registers, ie, flip-flop groups, connected to each other by a scan path;
b and 32b are registers at the final stage for setting an identification code consisting of a plurality of bits for failure detection, that is, a group of flip-flops. 6 is a mode register that holds a state for setting an identification code, a is a mode setting signal that sets mode register 3 to maintenance diagnosis mode, and b is an output signal of mode register 3 which is driven in maintenance diagnosis mode. 4 is an identification code writing means for setting an identification code; 4a is a write data line for propagating identification code data output from the identification code writing means 4;

FIGS. 4 and 5 are diagrams explaining details of this embodiment. 4 and 5, 41 to 43 are arbitrary LSI chips connected to the scan paths, respectively, similar to those shown in FIG.

[0012] When setting the maintenance diagnosis mode, an identification code 51 is embedded in advance in the final stage register in which an identification code consisting of a plurality of bits for failure detection is set.

Here, if all the LSI chips in the MCP are normal, the data input from the scan-in terminal is propagated onto the scan path as explained in FIGS. 1 and 2, and the data is processed as is. All are output from the scan-out terminal in the format (part diagram (A) in Figure 5).
)reference).

However, if a certain LSI chip in the MCP, for example, a register (flip-flop) in the LSI chip 42, is out of order, the signal embedded with the identification code 51 will not pass through the register as scan clock generating means. It passes by the number of stages of the campus (see division diagram (B) in Figure 5).

[0015] As a result, data divided by the identification code is obtained from the scan-out terminal, and by checking this data pattern, the failure location can be isolated for each LSI chip.

[0016]

[Effects of the Invention] As explained above, the failure detection method of the present invention adds an identification code to the scan path data by external mode setting, so that any LSI chip inside the MCP has failed, rather than for each MCP. This has the advantage that it can be easily detected without the need for large-scale hardware.

[Brief explanation of the drawing]

FIG. 1 is a block diagram schematically showing an embodiment of the present invention.

FIG. 2 is a diagram illustrating the embodiment of FIG. 1;

FIG. 3 is a perspective view showing the appearance of FIG. 1;

FIG. 4 is a diagram illustrating the embodiment of FIG. 1;

5A and 5B are diagrams for explaining the embodiment of FIG. 1; FIG.

[Explanation of symbols]

1 MCP (multi-chip package) 2
Scan path 3 Mode register 4 Identification data writing means 4a Write data lines 21 to 2C LSI chips 31, 32 LSI chips 31a, 32a Registers (flip-flops connected to each other) 31b, 32b Registers (flip-flops for setting identification code) 41 ~43 LSI chip 51 Identification code 52 Failure location a Mode setting signal b Mode signal

Claims (1)

[Claims] 1. A failure detection method for a multi-chip package in which a plurality of LSI chips each including a group of flip-flops are mounted and the groups of flip-flops are connected in cascade through a scan path, the method being set to a maintenance diagnosis mode when a failure occurs. a possible mode register, a data writing means for storing an identification code indicating a value specified at the time of setting the maintenance/diagnosis mode in the mode register in the final stage of the flip-flop group, and writing the identification code by applying a scan clock signal. A failure detection method characterized by comprising a connection means for sending out scan data as the next stage scan data.