JP2003084045A - Test device and method for semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simultaneously measure a number of pin devices with a small number of tester measuring terminals. SOLUTION: Two devices 1, 2 to be measured are provided with measured terminal decreasing circuits 3, 4. As for the measured device 1, output signals from x-number of output terminals 11 to 11x are input to EXOR gates 51 to 5x of the measured terminal decreasing circuit 3 and compared with the expected values 1 to x to detect coincidence or non-coincidence. When each comparison result is input to a NOR gate 71, a fail signal F1 for determining the measured device 1 is output and input to a tester measuring terminal 8. As for the measured device 2, similarly a fail signal F2 is output and input to the tester measuring terminal 8.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit test apparatus and method, and more particularly to a semiconductor integrated circuit test apparatus and method for simultaneously measuring multi-pin devices.

[0002]

2. Description of the Related Art FIG. 2 shows an example of the configuration of a conventional semiconductor integrated circuit testing apparatus, showing a case where two devices (semiconductor integrated circuits) are tested simultaneously. In FIG. 2, 1,
2 is a device to be measured, which has output terminals 11 to 1x,
21 to 2x. 8 is a measurement terminal of the tester, the number of terminals is the same as the number of the output terminals 11 to 1x, 21 to 2x, and all the output signals of the devices under test 1 and 2 are connected to the measurement terminal 8 of the tester. There is a need to. still,
As a conventional semiconductor integrated circuit testing apparatus and method, Japanese Patent Laid-Open No. 08-285925, "Testing method and apparatus for semiconductor integrated circuit", Japanese Patent Laid-Open No. 08-184646, "Semiconductor integrated circuit", Japanese Patent Laid-Open No. 2000-214235 are available. There are “Semiconductor integrated circuit device inspection method” and the like.

[0003]

In recent years, the number of pins of devices has been increased, and simultaneous measurement of a plurality of devices has become difficult. That is, there is a limit to the number of measurement terminals on the board of the tester, and simultaneous measurement was possible if the number of pins of multiple devices was within the number of measurement terminals of the board. Simultaneous measurement of pins was impossible or difficult.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor integrated circuit testing apparatus and method for simultaneously measuring multi-pin devices exceeding the number of measurement terminals of a tester. .

[0005]

In order to achieve the above object, in a semiconductor integrated circuit test apparatus according to the present invention, each output signal of a semiconductor integrated circuit under test having x output signals and x output signals are measured. The quality of the semiconductor integrated circuit to be measured is determined by taking the logical product of x comparison means for detecting the match / mismatch of the two by comparing each of the expected values of x and the comparison result of each of the x comparison means. AND means for outputting a determination signal for determination are provided.

Further, in the method for testing a semiconductor integrated circuit according to the present invention, each output signal of the semiconductor integrated circuit to be measured having x output signals is compared with x expected values, respectively. A coincidence / non-coincidence is detected, and a logical product of the detected comparison results is obtained to obtain a judgment signal for judging the quality of the semiconductor integrated circuit under test.

[0007]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit configuration diagram of a semiconductor integrated circuit testing device according to an embodiment of the present invention. In FIG. 1, 1 and 2 are devices to be measured, each of which has an output terminal 11
.About.1x, 21.about.2x. Each output signal of the device under test 1 is input to the measured terminal reduction circuit 3 and temporarily stored in the flip-flops 31 to 3x. Further, each output signal of the device under test 2 is input to the measured terminal reducing circuit 4 and temporarily stored in the flip-flops 41 to 4x.

On the other hand, a tester (not shown) supplies a clock to each flip-flop and inputs expected values 1 to x. The data stored in each flip-flop is input to the EXOR gates 51 to 5x and 61 to 6x together with the expected values 1 to x. The output of the EXOR gate is a logical value "0" when the two inputs match in each EXOR gate, and "1" when they do not match.

The outputs of the EXOR gates 51 to 5x are supplied to a NOR gate 71 having x input terminals. Therefore, if at least one logical value "1" is output from each EXOR gate, the output of the NOR gate 71 becomes a logical value "0" regardless of the logical values of the outputs of other EXOR gates. At this time, the logical value "0" is output as the output fail signal F1 for determining the quality of the device under test 1. This signal F1 is input to the tester measurement terminal 8.

Similarly, by applying the outputs of the EXOR gates 61 to 6x to the NOR gate 72 having x input terminals, at least one logical value "1" is output from each EXOR gate. For example, regardless of the logical values of the outputs of other EXOR gates, the output of the NOR gate 72 becomes the logical value "0", and at this time, the logical value "0" is output as the output fail signal F2 for judging the quality of the device under test 2. Is output. This signal F2 is input to the tester measurement terminal 8.

According to the present embodiment, in the function test of the same output, the circuits for reducing the number of terminals under test 3, 4 are measured.
It is possible to reduce the number of measurement terminals used on the tester side by unifying the output pins that output the same expected value for each device under test 1 and 2 by testing using It is possible to measure simultaneously and reduce the test time.

Here, as conditions for realizing the simultaneous measurement,
Simultaneous measurement of n devices, and the number of output signals of one device is 2 or more ・ Number of conventional input signals + (number of output signals × n) ≤ number of tester measurement terminals ・ Number of input signals of the present invention + number of output signals + N ≦ the number of tester measurement terminals.

In FIG. 1, the circuit for reducing the number of terminals to be measured has at least one NOR gate for each device to be measured.
However, the output signal of the EXOR gate is
It is also possible to output a plurality of output fail signals by dividing into groups and having a NOR gate for each group. If the EXOR gate and the NOR gate can configure the same logic, the EXNOR gate and the AND gate are used.
It is also possible to adopt a logic circuit based on the above. In the present invention, the NOR gate and the AND gate are used as the logical product means.

As for the output fail signal, the inversion logic of the above logic can be used as long as it is possible to determine a non-defective product and a defective product. Further, even in the case where a flip-flop is not adopted in the circuit for reducing terminals under test, the flip-flop can be omitted if the output fail signal is determined in consideration of the propagation time.

[0015]

As described above, according to the present invention, when the device under test which is the semiconductor integrated circuit to be tested is tested, the circuit for reducing the number of terminals under test is used.
Since the number of output of the determination signal can be reduced, it is possible to simultaneously measure a multi-pin device such as a plurality of devices, which can shorten the semiconductor test time and reduce the test cost.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a semiconductor integrated circuit test apparatus according to an embodiment of the present invention.

FIG. 2 is a configuration diagram showing a conventional semiconductor integrated circuit test apparatus.

[Explanation of symbols]

1, 2 Device under test Circuit for reducing the number of terminals to be measured 8 Tester measurement terminal 31-3x, 41-4x flip-flops 51-5x, 61-6x EXOR Gate 71, 72 NOR gate F1, F2 output fail signal

Claims (2)

[Claims] 1. Comparing each output signal of a semiconductor integrated circuit under test having x number of output signals with said x expected value, and comparing said x number of comparing means with said x number of comparing means. A logical product means for outputting a judgment signal for judging the quality of the semiconductor integrated circuit to be measured by taking the logical product of the respective comparison results by the x comparing means. Test equipment. 2. An output signal of a semiconductor integrated circuit to be measured having x output signals and the x expected values are respectively compared to detect a match / mismatch between the two, and each detected comparison result. A method of testing a semiconductor integrated circuit, wherein a determination signal for determining the quality of a semiconductor integrated circuit under test is obtained by taking a logical product of