JP3003781B2 - Inspection design method, bus error avoidance design method, and integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a design method for facilitating inspection of an integrated circuit and a bus error avoidance design method.

[0002]

2. Description of the Related Art In recent years, in the design of integrated circuits, AND
A tri-state element is used instead of an element or an OR element.

FIG. 19 is a diagram showing a tri-state element. FIG. 19 (a) is a symbol representing the tri-state element on a logic circuit diagram, and FIG. 19 (b) is a truth table showing the operation of the tri-state element. As shown in FIG. 19A, the tri-state element has an enable input EN in addition to the data input DIN and the data output DOUT. As shown in FIG. And an element having a function of switching between a mode in which the input terminal is output as it is and a mode in which the output terminal is set in a high impedance state without outputting the input data. That is, when the enable input EN is “1”, the data output DOUT is equal to the data input DIN, while when the enable input EN is “0”, the data output DOUT is the data input DIN.
"Z" (high impedance) regardless of the logical value of. Hereinafter, a state in which the tri-state element enters a mode in which input data is passed through and output as it is is referred to as a tri-state element being turned on, and a mode in which the tri-state element does not output input data and sets the output terminal to a high impedance state. That is, the tri-state element is turned off.

Conventionally, no test design method has been proposed for a scan design circuit including a tri-state element, and a circuit manufacturing side recommends a design that does not include a tri-state element to the design side. Was.

[0005]

However, heretofore, there have been the following problems.

First, the conventional scan design circuit including a tri-state element has a problem that it is impossible to detect the presence or absence of a failure of the enable input of the tri-state element.

For example, for a tri-state element whose data input DIN is "1", the enable input EN 1
In order to determine the presence / absence of the stuck-at fault, when the enable input EN is set to “0”, the data output DOUT becomes “1”.
Or “Z” must be observed and determined. However, if the data output DOUT is not directly connected to the external output terminal, it cannot be determined whether or not there is a failure.

Furthermore, not only the failure of the enable input of the tri-state element but also the failure of the logic circuit controlling only the enable input cannot be detected. For this reason, there is a problem that the failure detection rate of the integrated circuit is not improved.

When data outputs of a plurality of tri-state elements are connected to a common bus, a bus conflict caused by different output data of each tri-state element and all output terminals of each tri-state element have high impedance. There is a possibility that a bus error such as a bus float occurring due to the state may occur. To prevent such a bus error, when testing an integrated circuit, it is necessary to control the enable input of each tri-state element so that only one of the plurality of tri-state elements connected to the bus is turned on. is there.

However, in this case, it cannot be detected whether or not there is a failure in the data input of the tri-state element which is not turned on during the inspection. Further, it is impossible to detect the presence or absence of a failure in a logic circuit connected only to the data input. For this reason, there is a problem that the failure detection rate of the integrated circuit is not improved.

SUMMARY OF THE INVENTION In view of the above problems, an object of the present invention is to provide a design method for testability of an integrated circuit, which makes it possible to test a failure at a difficult-to-test position such as an enable input or a data input of a tristate element. I do.

Another object of the present invention is to provide a bus error avoidance design method capable of reliably preventing a bus error in an integrated circuit in which data output lines of a plurality of tri-state elements are connected to a common bus.

[0013]

Means for Solving the Problems To solve the above problems,
The solution taken by the invention of claim 1 is to make inspection easier.
As a design method, it is easy to inspect the failure of the integrated circuit.
The first step of scan design and the difficult or
Observe signals at locations that cannot be inspected, and observe the observed signals.
The observation circuit output from the scan flip-flop for
A second step of adding to the integrated circuit;
An output signal is output from the scan configured in the first step.
In order to be able to output from the integrated circuit via the chain,
Scans the scan flip-flop dedicated for observation
A third step of inserting into the chain,
The observation circuit includes a combination circuit that inputs a plurality of signals at locations that are difficult or untestable and that inputs an output signal to the scan flip-flop dedicated to observation. It is assumed that the output signal changes according to the change of the input signal.

According to the first aspect of the present invention, the integrated circuit is
It scanned designed in one step Rutotomoni, the second
In the process, communication of difficult or impossible
Observation signal and scan flip for observation signal
An observation circuit output from the flop is added. And
In the third step, an observation-only scan flip-flop
Group is inserted into the scan chain consisting of the scan design
Is done. This enables the tri-state device
In places where inspection such as input is difficult or where inspection is impossible
Inspection of a fault that has occurred depends on the scan configured by the scan design.
Observation from the external output terminal of the integrated circuit via the channel
Will be possible. Therefore, failure detection of integrated circuits is
Output rate and the output of the observation circuit
New external terminals for external observation of signals
No need. Further, since signals at a plurality of locations that are difficult to inspect or cannot be inspected can be observed through one observation-dedicated flip-flop, an increase in overhead due to the design for easy inspection can be suppressed. .

Further, in the invention of claim 2 , the above-mentioned claim is provided.
The combination circuit in the first design for testability method, 1
Or a plurality of exclusive ORs (EX
(OR) An EXOR tree composed of gates.

According to the third aspect of the present invention, in the first aspect,
In the combinational circuit in the testability designing method of (1), when the remaining input signal has a predetermined value, the output signal changes according to a change of one input signal.

[0017] A solution taken by the invention of claim 4
Inspects integrated circuits for faults as a design method for ease of inspection.
First step of scan design to make inspection easier and inspection
Observe and observe signals in difficult or untestable locations
Output from the dedicated scan flip-flop
A second step of adding an observation circuit to the integrated circuit;
The output signal of the observation circuit is configured in the first step.
Can be output from the integrated circuit via the configured scan chain
Scan flip-flop for observation only
And a third step of inserting
In addition, it is assumed that the portion which is difficult to inspect is a data input line of a tri-state element which does not output input data and is turned off when an integrated circuit is inspected.

According to the fourth aspect of the present invention, the integrated circuit is
The scan is designed in the first step, and the second
In the process, communication of difficult or impossible
Observation signal and scan flip for observation signal
An observation circuit output from the flop is added. And
In the third step, an observation-only scan flip-flop
Group is inserted into the scan chain consisting of the scan design
Is done. This enables the tri-state device
In places where inspection such as input is difficult or where inspection is impossible
Inspection of a fault that has occurred depends on the scan configured by the scan design.
Observation from the external output terminal of the integrated circuit via the channel
Will be possible. Therefore, failure detection of integrated circuits is
Output rate and the output of the observation circuit
New external terminals for external observation of signals
No need.

[0019] Further , a solution taken by the invention of claim 5 is as follows.
Inspects integrated circuits for faults as a design method for ease of inspection.
First step of scan design to make inspection easier and inspection
Observe and observe signals in difficult or untestable locations
Output from the dedicated scan flip-flop
A second step of adding an observation circuit to the integrated circuit;
The output signal of the observation circuit is configured in the first step.
Can be output from the integrated circuit via the configured scan chain
Scan flip-flop for observation only
And a third step of inserting
In the first step, a plurality of scan chains are formed in the integrated circuit, and in the third step, the maximum value of the number of scan flip-flops included in each scan chain does not increase. It is assumed that a scan flip-flop dedicated to observation is inserted.

According to the fifth aspect of the present invention, the integrated circuit is
The scan is designed in the first step, and the second
In the process, communication of difficult or impossible
Observation signal and scan flip for observation signal
An observation circuit output from the flop is added. And
In the third step, the observation dedicated scan flip front Tsu
Group is inserted into the scan chain consisting of the scan design
Is done. This enables the tri-state device
In places where inspection such as input is difficult or where inspection is impossible
Inspection of a fault that has occurred depends on the scan configured by the scan design.
Observation from the external output terminal of the integrated circuit via the channel
Will be possible. Therefore, failure detection of integrated circuits is
Output rate and the output of the observation circuit
New external terminals for external observation of signals
No need. Further, the number of test patterns required for testing a scan-designed integrated circuit depends on the maximum value of the number of scan flip-flops included in each scan chain. By inserting the scan flip-flop dedicated for observation so that the value does not increase, the failure detection rate of the integrated circuit can be improved without increasing the number of test patterns required for the test.

[0021] Further , a solution taken by the invention of claim 6 is as follows.
Inspects integrated circuits for faults as a design method for ease of inspection.
First step of scan design to make inspection easier and inspection
Observe and observe signals in difficult or untestable locations
Output from the dedicated scan flip-flop
A second step of adding an observation circuit to the integrated circuit;
The output signal of the observation circuit is configured in the first step.
Can be output from the integrated circuit via the configured scan chain
Scan flip-flop for observation only
And a third step of inserting
The first step is to configure a plurality of scan chains in an integrated circuit , and the third step is
In this step, observation-dedicated scan flip-flops are inserted so that the number of scan flip-flops included in each scan chain becomes equal.

According to the invention of claim 6 , the integrated circuit has
The scan is designed in the first step, and the second
In the process, communication of difficult or impossible
Observation signal and scan flip for observation signal
An observation circuit output from the flop is added. And
In the third step, the observation dedicated scan flip front Tsu
Group is inserted into the scan chain consisting of the scan design
Is done. This enables the tri-state device
In places where inspection such as input is difficult or where inspection is impossible
Inspection of a fault that has occurred depends on the scan configured by the scan design.
Observation from the external output terminal of the integrated circuit via the channel
Will be possible. Therefore, failure detection of integrated circuits is
Output rate and the output of the observation circuit
New external terminals for external observation of signals
No need. Further, since the number of test patterns required for testing a scan-designed integrated circuit depends on the maximum value of the number of scan flip-flops included in each scan chain, the number of scan flip-flops included in each scan chain is equal. By inserting the scan flip-flop dedicated for observation as much as possible, it is possible to improve the failure detection rate of the integrated circuit while minimizing the increase in the number of test patterns required for the test.

Further, the invention is of scan design according to claim 7
Operates only when the integrated circuit is inspected.
Scans including scan-only scan flip-flops
Chain is configured, the observation dedicated scan flip-flop, at the time of inspection of the integrated circuits, the data input signal of the tristate device turned off not to output the input data, it is an ordinary data input.

Further, according to the invention of claim 8 , the scan design
The integrated circuit operates only when the integrated circuit is inspected.
Scans including scan flip-flops dedicated to observation
Nchein is configured, the observation dedicated scan flip-flop is a multiple-input and one output, and is for receiving the output signal of the combination circuit output signal changes in response to changes in one input signal .

According to the ninth aspect of the present invention, the above-mentioned claim is provided.
It is assumed that the combinational circuit in the integrated circuit of No. 8 is an EXOR tree composed of a plurality of exclusive OR (EXOR) gates connected in one or a tree.

According to the tenth aspect of the present invention, the above-mentioned claim is provided.
In the combinational circuit of the eight integrated circuits, when the remaining input signals have a predetermined value, the output signal changes according to the change of one input signal.

According to the eleventh aspect of the present invention, the above-mentioned claim is provided.
It is assumed that the combinational circuit in the integrated circuit 8 receives the enable input signal of the tri-state element as an input.

According to the twelfth aspect of the present invention, the above-mentioned claim is provided.
It is assumed that the combinational circuit of the integrated circuit 8 receives a data input signal of a tri-state element which is turned off and does not output input data at the time of inspection of the integrated circuit.

According to a thirteenth aspect of the present invention, there is provided a bus state avoiding design method for changing a design of a scan-designed integrated circuit so that a bus error does not occur. Determining whether the enable input for the element is controlled by a scan flip-flop; from the integrated circuit,
A first process of extracting a bus connected to a data output terminal of a plurality of tri-state elements whose enable input is controlled by a scan flip-flop;
The output data of the scan flip-flop for controlling the enable input of the plurality of tri-state elements is input to the plurality of tri-state elements having the data output terminals connected to the bus extracted in the processing of the above, and the integrated circuit is inspected. When one of the plurality of tri-state elements
A second processing for generating a selection circuit for controlling an enable input of the plurality of tri-state elements so that only one of the plurality of tri-state elements is turned on to output through the input data; and
Arranging the selection circuit generated in the processing in the integrated circuit in the integrated circuit, and connecting output terminals of the arranged selection circuit to enable input terminals of the plurality of tri-state elements. The selection circuit generated in the process (1) receives the non-inverted output data and the inverted output data of the scan flip-flop for controlling the enable inputs of the plurality of tri-state elements. Shall be

According to the thirteenth aspect of the present invention, when testing an integrated circuit with respect to a plurality of tristate elements having a data output terminal connected to a common bus, only one of the plurality of tristate elements receives input data. Since a selection circuit for controlling the enable inputs of the plurality of tri-state elements is added so as to be in an on state in which the output is made through,
Bus errors that may occur when testing an integrated circuit can be prevented.

According to a fourteenth aspect of the present invention, there is provided an integrated circuit which is scan-designed and whose design is changed so that a bus error does not occur, a plurality of data output terminals connected to a common bus. The output data of the scan flip-flop is input to the tri-state element, and when inspecting the integrated circuit, the plurality of tri-state elements are turned on such that only one of the plurality of tri-state elements passes through the input data and is output. A selection circuit for controlling an enable input of the tri-state element is arranged, and the selection circuit receives normal output data and inverted output data of the scan flip-flop as inputs.

[0032]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a flowchart showing the outline of a design method for testability according to the present invention. As shown in FIG. 1, the design method for testability according to the present invention includes a first step S1 of scan-designing a given integrated circuit so that a failure test is easy, and observing a signal at a place where inspection is difficult. Then, a second step S2 for adding an observation circuit that outputs an observed signal from the scan flip-flop dedicated to observation to the integrated circuit scanned and designed in the first step S1, and an observation circuit added in the second step S2. The output signal is the first step S
And a third step S3 of inserting the observation-only scan flip-flop (observation-only scan FF) into the scan chain so that the integrated circuit can output from the integrated circuit via the scan chain configured in 1.

The first step S1 is performed according to a conventionally well-known scan design technique. The design method for testability according to the present invention applies the second and third processes to the integrated circuit scan-designed in the first process S1.
2. In S3, the design is changed to further improve the failure detection rate.

Hereinafter, embodiments of the design method for testability according to the present invention will be described with reference to the drawings.

(First Embodiment) In a first embodiment of the present invention, a scan-designed integrated circuit including a tri-state element can be easily inspected for a failure of a logic circuit for controlling an enable input of the tri-state element. The design is changed to become.

FIG. 2 is a flowchart showing the flow of processing in the testability design method according to the present embodiment, and corresponds to the second and third steps S2 and S3.
Steps S11 to S15 constitute a second step S2, and step S16 constitutes a third step S3.

First, in step S11, for an given integrated circuit, an EXOR tree whose number of inputs is equal to the number of all tri-state elements in the integrated circuit, and one observation-dedicated scan FF are observed. Generate as a circuit. Here, the EXOR tree is composed of one or a plurality of exclusive OR (EXOR) circuits connected in a tree shape.

Next, in step S12, it is determined whether a tri-state element not yet connected to the input of the EXOR tree generated in step S11 exists in the integrated circuit. If it exists, the process proceeds to step S13. If it does not exist, the process proceeds to step S15.

In step S13, one tristate element not yet connected to the input of the EXOR tree is selected. Then, in step S14, the enable input of the tri-state element selected in step S13 is connected to the input of the EXOR tree generated in step S11. By repeating steps S12 to S14, the enable inputs of all the tri-state elements in the integrated circuit are connected to the inputs of the EXOR tree generated in step S11.

In step S15, step S11
Is connected to the normal data input of the scan FF for observation generated in step S11. Then, in step S16, the observation-dedicated scan FF is inserted into an arbitrary portion of the scan chain already configured in the first step S1.

The testability design method according to the present embodiment will be described in more detail by taking a simple circuit as an example.

FIGS. 3A and 3B are diagrams for explaining the testability design method according to the present embodiment, in which FIG. 3A is a circuit diagram showing a circuit to be designed for testability, and FIG. FIG. 6 is a circuit diagram showing a circuit obtained as a result of performing the design for testability by the testability design method according to the present embodiment on the circuit shown in FIG.

In FIG. 3A, reference numerals 11 and 12 denote tristate elements, and reference numerals 13 and 14 denote logic circuits for controlling enable inputs of the tristate elements 11 and 12, respectively.
5 is an inverter.

With respect to the circuit shown in FIG. 3A, first, in step S11, an observation circuit 10 including an EXOR tree 16 and an observation-dedicated scan FF 17 is generated. FIG.
The circuit shown in (a) has two tri-state elements 11,
12, the EXOR tree 16 has two inputs. That is, the EXOR tree 16 has one EXO tree.
It is constituted by an R gate 16a.

Next, in steps S12 to S14,
EX enable input of tristate elements 11 and 12
It is connected to the input of the OR tree 16 and in step S15, the output of the EXOR tree 16 is
17 normal data input D.

Finally, in step S16, the observation-dedicated scan FF 17 is inserted into the existing scan chain 18 including the scan FFs 18a and 18b. As shown in FIG. 3B, the connection between the output Q of the scan FF 18a and the test data input DT of the scan FF 18b is disconnected, and the output Q of the scan FF 18a is connected to the test data input DT of the observation-dedicated scan FF 17. In addition, the output Q of the dedicated scan FF 17 and the scan F
F18b is connected to the test data input DT.

In the circuit shown in FIG. 3B whose design has been changed in this way, the presence or absence of a failure in the logic circuits 13 and 14 is observed from an external output pin via the observation dedicated scan FF 17 and the scan chain 18. Can be.

FIG. 4 is a diagram showing another example of the EXOR tree used in the observation circuit according to the present embodiment. In the figure, (a) is a four-input E composed of three EXOR gates.
The XOR tree, (b) is a 7-input EXOR tree composed of six EXOR gates.

As described above, according to the testability design method according to the first embodiment of the present invention, the enable input of the tri-state element in the integrated circuit is connected to the input of the EXOR tree, By connecting the output to the existing scan chain via the observation dedicated scan FF, it is possible to observe from the external output pin whether there is a failure in the logic circuit that controls only the enable input of the tri-state element, which could not be observed conventionally. Because
The fault detection rate of the integrated circuit can be improved.

(Modification of First Embodiment) In the first embodiment, the case where the observation circuit is formed by using the EXOR tree has been described. However, a combination circuit having a plurality of inputs and one output other than the EXOR tree is used. An observation circuit may be configured. In the testability design method according to this modification, an observation circuit is configured using a NAND tree including NAND gates.

FIG. 5 is a circuit diagram showing the result of the design for testability performed by the testability design method according to this modification. In FIG. 5, an observation circuit 70 for observing enable inputs of the tri-state elements 81 to 84 includes a NAN.
NAND tree 71 composed of D gates 71a to 71c
And an observation-dedicated scan FF 72.

In the circuit shown in FIG. 5, for example, the observation circuit 7
When observing the enable input of the tri-state element 81 with 0, the enable input signal of the tri-state element 82 must be set to "1" and the enable input signals of the tri-state elements 83 and 84 must be set to "0". . In other words, unless the integrated circuit can set the output signal of the logic circuit 86 to “1” and simultaneously set the output signals of the logic circuits 87 and 88 to “0”, the NA
The observation circuit 70 including the ND tree 71 cannot observe the enable input of the tri-state element 81.

The multiple-input, one-output combination circuit used in the observation circuit must be such that the output signal changes in response to a change in one input signal, that is, a change in one input propagates to the output. E according to the first embodiment
The XOR tree and the NAND tree according to this modification are common in that they are a combination circuit of a plurality of inputs and one output in which a change in one input propagates to an output. However, EXO
In the R tree, a change in one input propagates to the output irrespective of the value of the remaining input, whereas in the NAND tree, when the remaining input has a predetermined value, as shown in this modification. Only one input change propagates to the output. Therefore, the EXOR tree can be used without being restricted by the configuration of the integrated circuit, and has higher versatility than other combinational circuits such as a NAND tree. On the other hand, in the NAND tree, the NAND gate has a simpler transistor-level configuration than the EXOR gate, and therefore has a smaller circuit area than the EXOR tree. Therefore, the NAND tree is suitable for suppressing an increase in overhead due to the design for testability.

It is to be noted that any combination circuit other than the EXOR tree or the NAND tree can be used for the observation circuit as long as it is a combination circuit of a plurality of inputs and one output in which a change of one input propagates to the output.

(Second Embodiment) A second embodiment of the present invention is similar to the first embodiment,
The purpose of the present invention is to redesign a scan-designed integrated circuit including a tri-state element so that a failure of a logic circuit that controls an enable input of the tri-state element is easily inspected.

FIG. 6 is a flowchart showing the flow of processing in the testability design method according to the present embodiment, and corresponds to the second and third steps S2 and S3.
Steps S21 to S24 constitute a second step S2, and step S25 constitutes a third step S3.

First, in step S21, for a given integrated circuit, a number of observation-dedicated scan FFs equal to the number of all tri-state elements in the integrated circuit are generated as observation circuits.

Next, in step S22, it is determined whether or not a tri-state element that is not connected to the observation dedicated scan FF generated in step S21 exists in the integrated circuit. If it exists, the process proceeds to step S23. If it does not exist, the process proceeds to step S25.

In step S23, step S21
One tri-state element not yet connected to the observation-dedicated scan FF generated in step is selected. Then, in step S24, the enable input of the tristate element selected in step S23 is connected to the normal data input of the observation-dedicated scan FF generated in step S21 that is not yet connected to the tristate element. By repeating steps S22 to S24, the enable inputs of all the tri-state elements in the integrated circuit become
It is connected to the normal data input of each observation dedicated scan FF generated in step S21.

In step S25, this observation-dedicated scan FF is inserted into an arbitrary portion of the scan chain already configured in the first step S1.

The testability design method according to the present embodiment will be described in more detail by taking a simple circuit as an example.

FIG. 7 is a diagram for explaining the testability design method according to the present embodiment. For the circuit shown in FIG. 3A, testability is improved by the testability design method according to the present embodiment. FIG. 9 is a circuit diagram showing a circuit as a result of performing an integrated design.

In the circuit shown in FIG. 3A, first, in step S21, scan FFs 21 and 22 dedicated to observation are used.
Is generated. Here, FIG.
Since the circuit shown in FIG. 2 includes two tri-state elements 11 and 12, two scan-only scan FFs 21 and
22 is generated.

Next, in steps S22 to S24,
The enable inputs of the tri-state elements 11 and 12 are connected to the normal data input D of the scan-only scan FFs 21 and 22, respectively.

Then, in step S25, the scan FFs 21 and 22 dedicated to observation are changed to the scan FFs 18a and 18
b) is inserted into the existing scan chain 18 composed of. As shown in FIG. 7, the connection between the output Q of the scan FF 18a and the test data input DT of the scan FF 18b is disconnected, and the output Q of the scan FF 18a is connected to the test data input DT of the scan FF 21 dedicated to observation, and the data dedicated to observation DT 21 is connected. The output Q of the scan FF 21 is connected to the inspection data input DT of the observation dedicated scan FF 22, and the output Q of the observation dedicated scan FF 22 and the scan FF 18 are connected.
b and the test data input DT.

In the circuit shown in FIG. 7 whose design has been changed in this way, the presence / absence of a failure in the logic circuits 13 and 14 for controlling the enable inputs of the tristate elements 11 and 12 is determined by observing scan FFs 21 and 22 and a scan chain 18.
Via the external output pin.

As described above, according to the testability design method according to the second embodiment of the present invention, the enable input of the tri-state element in the integrated circuit is connected to the normal data input of the scan FF for observation only. Accordingly, the presence or absence of a failure of the logic circuit that controls only the enable input of the tri-state element, which cannot be observed in the related art, can be observed from the external output pin, so that the failure detection rate of the integrated circuit can be improved.

In the first and second embodiments, all the tri-state elements of the integrated circuit are targeted for easy inspection. However, a part of the tri-state elements included in the integrated circuit may be targeted.

Note that the first and second embodiments may be combined. In other words, the observation circuit, a part of which is EX
The configuration may be made by using a combination circuit of a plurality of inputs and one output such as an OR tree, and the other portions may be configured by directly connecting an observation-dedicated scan FF to an enable input of a tri-state element.

Third Embodiment In a third embodiment of the present invention, a scan-designed integrated circuit including a tri-state element is connected to a logic connected to a data input of a tri-state element which is turned off during inspection. The design is changed so that inspection for circuit failure is facilitated.

FIG. 8 is a flowchart showing the flow of processing in the testability design method according to the present embodiment, and corresponds to the second and third steps S2 and S3.
Steps S31 to S36 constitute a second step S2, and step S37 constitutes a third step S3.

For a given integrated circuit, first, in step S31, it is determined whether or not each of the tri-state elements in the integrated circuit is turned off during the test, and all the tri-state elements that are turned off during the test are determined. Is extracted.

Next, in step S32, an EXOR tree having the number of inputs equal to the number of tri-state elements extracted in step S31 and one observation-dedicated scan FF are generated as an observation circuit.

Then, in step S33, it is determined whether or not there is a tri-state element that is not connected to the input of the EXOR tree generated in step S32.
If it exists, the process proceeds to step S34. If it does not exist, the process proceeds to step S36.

In step S34, one of the tri-state elements not connected to the input of the EXOR tree is selected. Then, in step S35, the data input of the tri-state element selected in step S34 is connected to the input of the EXOR tree generated in step S32. By repeating steps S33 to S35, the data input of all the tri-state elements extracted in step S31 becomes the EXOR generated in step S32.
Connected to tree input.

Next, in step S36, the output of the EXOR tree generated in step S32 is output to step S3.
Connect to the normal data input of the observation dedicated scan FF generated in step 2. Finally, in step S37, this observation-dedicated scan FF is inserted into an arbitrary position of the scan chain already configured in the first step S1.

The testability design method according to the present embodiment will be described in more detail by taking a simple circuit as an example.

FIGS. 9 and 10 are diagrams for explaining the testability design method according to the present embodiment. FIG. 9 is a circuit diagram showing a circuit to be designed for testability, and FIG. FIG. 9 is a circuit diagram showing a circuit obtained as a result of performing the design for testability by the testability design method according to the present embodiment for the circuit shown in FIG.

In FIG. 9, reference numerals 31, 32, and 33 denote tristate elements, and reference numerals 34, 35, and 36 denote logic circuits connected to the data inputs of the tristate elements 31, 32, and 33, respectively. In the circuit shown in FIG. 9, only the tri-state element 31 is turned on during the inspection, and the tri-state element 3 is turned on.
2, 33 are turned off. That is, when inspecting the circuit shown in FIG. 9, a logical value "1" is given to the enable input of the tristate element 31, while a logical value "0" is given to the enable inputs of the tristate elements 32 and 33. Can be

In the circuit shown in FIG. 9, first, in step S31, tri-state elements 32 and 33 that are turned off during inspection are extracted.

Next, in step S32, an observation circuit 30 including an EXOR tree 38 and an observation-dedicated scan FF 39 is generated. Here, since the two tri-state elements 32 and 33 are extracted in step S31, the EXOR tree 38 has two inputs. That is, EXOR tree 3
8 is constituted by one EXOR gate 38a.

Next, in steps S33 to S35, the data inputs of the tri-state elements 32 and 33 are connected to the inputs of the EXOR tree 38. Then, in step S36, the output of the EXOR tree 38 is connected to the normal data input of the observation dedicated scan FF 39.

Finally, in step S37, the observation-dedicated scan FF 39 is inserted into the existing scan chain 18 composed of the scan FFs 18a and 18b. As shown in FIG. 10, the output Q of the scan FF 18a is
Is disconnected from the inspection data input DT of the scan FF 18b, the output Q of the scan FF 18a is connected to the inspection data input DT of the observation dedicated scan FF 39, and the output Q of the observation dedicated scan FF 39 and the scan FF are connected.
18b is connected to the test data input DT.

In the circuit shown in FIG. 10 whose design has been changed in this way, the tri-state elements 32, 3 which are turned off during inspection
The presence / absence of a failure in the logic circuits 35 and 36 connected to the data input of No. 3 can be observed from an external output pin through the observation dedicated scan FF 39 and the existing scan chain 18.

As described above, according to the testability design method according to the third embodiment of the present invention, the data input of the tri-state element which is turned off during the test is connected to the input of the EXOR tree, and this EXOR tree is connected. By connecting the output of the tree to the existing scan chain via the scan FF dedicated to observation, the failure of the logic circuit connected only to the data input of the tri-state element that is turned off during the inspection, which could not be observed conventionally, can be detected. The presence / absence can be observed from the external output pin. Thereby, the failure detection rate of the integrated circuit can be improved.

(Fourth Embodiment) A fourth embodiment of the present invention is similar to the third embodiment,
The design of a scan-designed integrated circuit including a tri-state element is changed so that a failure of a logic circuit connected to a data input of the tri-state element which is turned off during inspection can be easily inspected.

FIG. 11 is a flowchart showing the flow of processing in the testability design method according to this embodiment.
This corresponds to the second and third steps S2 and S3. Steps S41 to S45 constitute a second step S2, and step S46 constitutes a third step S3.

For a given integrated circuit, first, in step S41, it is determined whether or not each tri-state element in the integrated circuit is turned off during the test, and all the tri-states that are turned off during the test are determined. Extract elements.

Next, in step S42, as many observation-dedicated scan FFs as observation circuits are generated, the number being equal to the number of tri-state elements extracted in step S41.

In step S43, step S42
It is determined whether or not a tri-state element not yet connected to the observation-dedicated scan FF generated in step 3 exists in the integrated circuit. If there is, go to step S44,
If not, the process proceeds to step S46.

In step S44, step S42
One tri-state element not yet connected to the observation-dedicated scan FF generated in the step is selected. In step S45, the data input of the tri-state element selected in step S44 is connected to the normal data input of the observation-dedicated scan FF generated in step S42 that is not yet connected to the tri-state element. By repeating steps S43 to S45, the data inputs of all the tri-state elements extracted in step S41 are connected to the normal data inputs of the observation dedicated scan FF generated in step S42.

Finally, in step S46, each observation-dedicated scan FF is inserted into an arbitrary portion of the scan chain already configured in the first step S1.

The testability design method according to the present embodiment will be described with respect to a case where the circuit shown in FIG. 9 is used as an example.
This will be described in more detail.

FIG. 12 is a circuit diagram showing a circuit obtained as a result of the design for testability performed on the circuit shown in FIG. 9 by the testability design method according to the present embodiment.

In the circuit shown in FIG. 9, first, in step S41, the tri-state elements 32 and 33 which are turned off during inspection are extracted.

Next, in step S42, an observation circuit 40 including scan FFs 41 and 42 dedicated to observation is generated. In step S41, the two tri-state elements 32,
Since 33 are extracted, two scan FFs 41 and 42 dedicated to observation are generated here.

Next, in steps S43 to S45, the data inputs of the tristate elements 32 and 33 are connected to the normal data inputs D of the scan FFs 41 and 42 for observation only, respectively.

Finally, in step S46, the scan FFs 41 and 42 dedicated to observation are changed to the scan FFs 18a and 18
b) is inserted into the existing scan chain 18 composed of. As shown in FIG. 12, the connection between the output Q of the scan FF 18a and the test data input DT of the scan FF 18b is disconnected, and the output Q of the scan FF 18a is connected to the test data input DT of the scan FF 41 dedicated to observation. The output Q of the dedicated scan FF 41 and the inspection data input DT of the dedicated scan FF 42 are connected, and the output Q of the dedicated scan FF 42 and the scan FF are connected.
18b is connected to the test data input DT.

In the circuit shown in FIG. 12 whose design has been changed in this way, the tri-state elements 32, 3 which are turned off during the test are provided.
The presence or absence of a failure in the logic circuits 35 and 36 connected to the data input of No. 3 can be observed from the external output pins via the scan FFs 41 and 42 for observation and the existing scan chain 18.

As described above, according to the testability design method according to the fourth embodiment of the present invention, the data input of the tri-state element that is turned off during the test is connected to the normal data input of the observation-dedicated scan FF. By doing so, it becomes possible to observe from the external output pin whether or not there is a failure in the logic circuit connected only to the data input of the tri-state element that is turned off during the test, which could not be observed conventionally. Therefore, the failure detection rate of the integrated circuit can be improved.

Note that the design method for testability according to the present invention is not limited to the failure of the portion related to the enable input and data input of the tri-state element as shown in the first to fourth embodiments. It is also applicable to faults other than those difficult to inspect, that is, untestable faults and undetected faults.

FIG. 13 is a flow chart showing the flow of processing in the testability designing method according to the present invention for untestable faults and undetected faults. Step SA1
SA5 constitutes a second step S2, and step SA6 constitutes a third step S3.

For a given integrated circuit, first, in step SA1, a test sequence is generated. Then, in step SA2, it is determined whether an untestable fault or an undetected fault exists in the integrated circuit. If it does not exist, the process ends. If it exists, the process proceeds to step SA3.

In steps SA3 to SA5, an observation-dedicated scan FF is added to untestable faults or undetected faults in the integrated circuit.

FIG. 14 is a diagram for explaining the testability design method according to the present invention for untestable faults and undetected faults. FIG. 14A shows an example of a circuit having untestable faults. (B) is a circuit diagram showing the result of performing the testability design on the circuit of (a).

In FIG. 14A, the selector 45 selects one of the output signals of the circuit 1 and the circuit 2 by a signal input to the external input terminal 46, and outputs the selected signal to the circuit 3. Here, assuming that the input signal of the external input terminal 46 is fixed to a logical value such that the output signal of the circuit 2 is selected by the selector 45 during the inspection of the circuit.
The failure of the circuit 1 cannot be detected at all. That is, an untestable failure occurs.

In order to make the circuit 1 inspectable,
As shown in FIG. 14B, the observation-dedicated scan FF 48
Is added, and the output line of the circuit 1 is connected to the observation exclusive scan FF 48.
To the data input D of

Finally, in step SA6, the added observation dedicated scan FF 48 is inserted into the existing scan chain 18 in the integrated circuit. As a result, untestable faults can be checked via the scan chain 18.

Note that, instead of directly connecting the observation-dedicated scan FF to the untestable failure point, the observation-dedicated scan FF may be connected via an EXOR tree as in the first or third embodiment. Of course, the connection may be made via another combination circuit of a plurality of inputs and one output.

Here, the assignment of the scan FF dedicated to observation in the third step S3 to the scan chain will be described.

In the third step S3, the scan FF dedicated to observation of the observation circuit added in the second step S2 is inserted into the scan chain already configured in the first step S1. However, actually, since a plurality of scan chains are configured by the scan design, in the third step S3, it is necessary to determine in which scan chain the observation-dedicated scan FF is to be inserted.

On the other hand, the number of test patterns required for testing a scan-designed integrated circuit depends on the maximum number of scan FFs in each scan chain. That is, the larger the maximum value of the number of scan FFs included in each scan chain, the larger the number of inspection patterns required for inspection. Therefore, here
The assignment of the scan FF dedicated to observation to the scan chain is determined so that the number of test patterns required for the test does not increase as much as possible.

Now, it is possible to add 3
It is assumed that scan chains CA, CB, and CC are configured, and the number of scan FFs included in each scan chain is as follows.

Scan chain CA... 500 Scan chain CB... 450 Scan chain CC... 480 At this time, allocation of observation-dedicated scan FFs to be inserted is performed as follows according to the number. (A) When the number of scan FFs dedicated to observation is 70 or less Insert the scan FFs so that the maximum value of the number of scan FFs in each scan chain does not change. For example, if there are 60 observation-dedicated scan FFs, 50
And ten are inserted into the scan chain CC. As a result, the maximum value of the number of scan FFs in each scan chain does not change and remains unchanged at 500, so that the number of inspection patterns required for inspection does not increase. (B) When the number of scan FFs dedicated to observation exceeds 70 Insert the scan FFs so that the number of scan FFs in each scan chain is equal. Specifically, the total number of scan FFs of the scan chains CA, CB, and CC (143
0 = 500 + 450 + 480) Scan FF dedicated to observation
Is divided by the number of scan chains, so that the number of scan FFs including the scan-only scan FF included in each scan chain becomes the quotient. For example, when the number of observation-dedicated scan FFs is 130, the quotient is 520 (= (1430 + 130) / 3), so that 20 scan scan CAs, 70 scan chain CBs, and 40 scan chain CCs Insert As a result, the number of scan FFs included in each scan chain becomes equal to 520, the maximum value of the number of scan FFs included in each scan chain is suppressed to a minimum of 20, and the number of inspection patterns required for inspection is reduced. Increase is minimal.

FIG. 15 is a circuit diagram schematically showing a configuration of an integrated circuit designed for testability by the testability design method according to the present invention. In FIG. 15, reference numeral 91 denotes a scan chain formed between external terminals 91a and 91b;
Reference numeral 92 denotes a scan chain formed between the external terminals 92a and 92b, reference numerals 93a to 93e denote tristate elements, and an enable input of the tristate elements 93c and 93e is set to "0" at the time of inspection. Observation-only scan FFs 95a and 95b are inserted into the scan chain 91, and observation-only scan FFs 95c are inserted into the scan chain 92.

The scan FF 95a for exclusive use of observation is EXOR
The output signal of the tree 94 is input and the EXOR tree 94
Inputs the enable input signals of the tristate elements 93a and 93b and the data input signal of the tristate element 93c. The observation-dedicated scan FF 95b receives the enable input signal of the tri-state element 93d as an input, and the observation-dedicated scan FF 95c receives the data input signal of the tri-state element 93e as an input.

(Fifth Embodiment) The fifth embodiment of the present invention is applicable to a case where data outputs of a plurality of tri-state elements controlled by scan FFs in an integrated circuit are connected to a common bus. The present invention relates to a bus error avoidance design method for surely preventing an error.

FIG. 16 is a flowchart showing the flow of processing in the bus error avoidance design method according to the fifth embodiment of the present invention.

For the given integrated circuit, first, in step S51, it is determined whether or not the enable inputs of all the tri-state elements in the integrated circuit are controlled by the scan FF.
The bus connected to the data output of the plurality of tri-state elements controlled by F is extracted.

Next, in step S52, it is determined whether or not any of the buses extracted in step S52 has not been subjected to the bus error avoiding process. If there is, the process proceeds to step S53, and if not, the process ends.

In step S53, one bus that has not been subjected to the bus error avoiding process is selected. In step S54, for the bus selected in step S53, a selection circuit is generated that controls the enable input of each tristate element so that only one of the plurality of tristate elements connected to the bus is turned on during inspection. Then, in step S55, the selection circuit generated in step S54 is connected to the enable input of the tri-state element connected to the bus selected in step S53.

The bus error avoiding design method according to the present embodiment will be described with respect to a simple circuit as an example.
This will be described in more detail.

FIGS. 17A and 17B are diagrams for explaining the bus error avoiding design method according to the present embodiment. FIG. 17A is a circuit diagram showing a circuit in which a bus error may occur, and FIG. FIG. 6 is a circuit diagram showing a circuit obtained as a result of avoiding a bus error by using the bus error avoidance design method according to the present embodiment for the circuit shown in FIG. In FIG. 17A, 5
Reference numerals 1 and 52 denote tristate elements whose data outputs are both connected to the bus 50, and 53 and 54 denote scan FFs for controlling enable inputs of the tristate elements 51 and 52, respectively.

First, with respect to the circuit shown in FIG.
In step S51, the bus 50 to which the data input of the tri-state element 51 whose enable input is controlled by the scan FF 53 and the data output of the tri-state element 52 whose enable input is controlled by the scan FF 54 are connected is extracted.

Then, in steps S52 to S55, the selection circuit 56 is generated and the tristate element 51,
Connect to 52 enable input. The selection circuit 56 includes a three-input AND gate 56a, a three-input OR gate 56b, and an inverter 56c.
Of the scan FF 53,
During the shift operation of 54, the enable inputs of the tristate elements 51 and 52 are controlled so that the tristate element 51 is turned off and the tristate element 52 is turned on.

On the other hand, FIG. 18A is a circuit diagram showing a circuit in which a bus error avoidance design has been performed on the circuit shown in FIG. 17A by a conventional method (Mentor Graphics).
DFTADVISOR reference manual, ver8.4.1,1994,7
Month). In FIG. 18A, the tri-state element 5
Between the scan FFs 1 and 52 and the scan FFs 53 and 54, a selection circuit 66 generated by a bus error avoidance design is inserted.

The selection circuit 66 includes scan FFs 53 and 54.
And the mode switching signal NT of the scan FF, and outputs a signal to the enable input of the tri-state elements 51 and 52. The scan FFs 53 and 54 are used to prevent a bus error from occurring in the bus 50.
During the shift operation, the tristate elements 51 and 52 are controlled so that the tristate element 51 is turned off and the tristate element 52 is turned on.

However, when a circuit such as the selection circuit 66 is used to avoid a bus error, the normal data inputs of the scan FFs 53 and 54 both have the logical value "1" when the shift operation is completed. When the mode switching signal NT is set to "L" to perform the capture operation as shown in FIG. 18B, the logic value of the enable input of the tri-state elements 51 and 52 is set to "1" for a half clock (period TA). "Become. Therefore, a bus conflict occurs in the bus 50.

Therefore, in the present embodiment, the selection circuit 56 outputs the normal output data Q and the inverted output data N of each scan FF.
Q are input to each other, and a logic is formed so that the tri-state elements 51 and 52 are not simultaneously turned on even during the normal operation of the scan FF.

In the circuit shown in FIG. 17B whose design has been changed in this way, a bus error such as a bus conflict or a bus float does not occur in the bus 50 during the inspection.

As described above, according to the bus error avoidance design method according to the fifth embodiment of the present invention, an integrated circuit having a bus to which data outputs of a plurality of tri-state elements controlled by scan FFs are connected For one of the plurality of tri-state elements connected to the bus.
By inserting a selection circuit that controls the enable input of each tri-state element so that only one is turned on, a bus error can be prevented beforehand.

[0132]

As described above, according to the present invention, an integrated circuit is scan-designed, and an observation circuit for observing a part difficult to inspect is newly added, and a scan flip-flop dedicated to observation of this observation circuit is designed by scan design. By inserting it into the configured scan chain, it is possible to inspect a failure at a difficult-to-check place such as an enable input of a tri-state element from the external output terminal of the integrated circuit via the scan chain. Therefore, the failure detection rate of the integrated circuit can be improved as compared with the related art. Moreover, there is no need to newly provide an external terminal for externally observing the output signal of the observation circuit.

[Brief description of the drawings]

FIG. 1 is a flowchart showing an outline of a testability design method according to the present invention.

FIG. 2 is a flowchart showing a processing flow of a testability design method according to the first embodiment of the present invention.

3A and 3B are diagrams for explaining a testability design method according to the first embodiment of the present invention, wherein FIG. 3A is a circuit diagram showing a circuit to be tested and designed, and FIG. FIG. 9 is a circuit diagram showing a circuit obtained as a result of performing testability design on the circuit of FIG.

FIGS. 4A and 4B are examples of the configuration of an EXOR tree.

FIG. 5 is a circuit diagram showing a circuit obtained as a result of the design for testability performed by the testability design method according to the modification of the first embodiment of the present invention.

FIG. 6 is a flowchart showing a processing flow of a testability design method according to a second embodiment of the present invention.

FIG. 7 is a diagram for explaining a testability design method according to the second embodiment of the present invention; FIG. 7A is a circuit diagram of FIG. FIG. 9 is a circuit diagram showing a circuit as a result of performing an integrated design.

FIG. 8 is a flowchart showing a processing flow of a testability design method according to a third embodiment of the present invention.

FIG. 9 is a diagram for explaining a testability design method according to a third embodiment of the present invention, and is a circuit diagram illustrating a circuit to be tested and designed;

10 is a diagram for explaining a testability design method according to the third embodiment of the present invention, and is a circuit diagram showing a circuit obtained as a result of the testability design performed on the circuit of FIG. 9; is there.

FIG. 11 is a flowchart showing a processing flow of a testability design method according to a fourth embodiment of the present invention.

FIG. 12 is a diagram for explaining a testability design method according to a fourth embodiment of the present invention, and is a circuit diagram showing a circuit as a result of performing testability design on the circuit of FIG. 9; is there.

FIG. 13 is for an untestable fault and an undetected fault.
5 is a flowchart showing a flow of processing in the testability design method according to the present invention.

FIG. 14 is a diagram for untestable faults and undetected faults.
BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A and 1B are diagrams for explaining a testability design method according to the present invention, wherein FIG. 1A is a circuit diagram showing an example of a circuit having an untestable fault, and FIG. FIG. 9 is a circuit diagram showing a result of performing a design for conversion.

FIG. 15 is a diagram schematically showing a configuration of an integrated circuit as a result of performing the design for testability by the testability design method according to the present invention.

FIG. 16 is a flowchart showing a processing flow in a bus error avoidance design method according to a fifth embodiment of the present invention.

17A and 17B are diagrams for explaining a bus error avoidance design method according to the fifth embodiment of the present invention, wherein FIG. 17A is a circuit diagram showing a circuit in which a bus error may occur, and FIG. FIG. 9 is a circuit diagram showing a circuit resulting from avoiding a bus error for the circuit shown in FIG.

18A and 18B are diagrams for explaining a conventional bus error avoidance design method, in which FIG. 18A is a circuit diagram showing a circuit on which a bus error avoidance design is performed, and FIG. 18B is a diagram showing a scan in the circuit shown in FIG. FIG. 3 is a timing chart showing a clock and a signal NT supplied to an FF.

FIGS. 19A and 19B are diagrams showing a tri-state element, and FIG.
Is a symbol representing a tristate element on a logic circuit diagram,
(B) is a truth table showing the operation of the tri-state element.

[Explanation of symbols]

10,20,30,40,70 Observation circuit 11,12,31,32,33,81,82,83,8
4, 93a, 93b, 93c, 93d, 93e Tri-state element 13, 14, 34, 35, 36, 85, 86, 87, 8
8 Logic circuit 16, 38, 94 EXOR tree 17, 21, 22, 39, 41, 42, 48, 72, 9
5a, 95b, 95c Scan flip-flop dedicated to observation 18, 91, 92 Scan chain 50 Bus 51, 52 Tri-state element 53, 54 Scan flip-flop 56 Selection circuit

Claims (14)

(57) [Claims] An integrated circuit can be easily inspected for failure.
The first step in scan design, and observing and observing signals at locations that are difficult or impossible to inspect.
The measured signal is output from the scan flip-flop dedicated to observation.
A second step of adding an energizing observation circuit to said integrated circuit
And the output signal of the observation circuit is configured in the first step.
Can be output from the integrated circuit via the configured scan chain
Scan flip-flop for observation only
And a third step of inserting
The observation circuit includes a combinational circuit that inputs a plurality of signals at locations that are difficult to inspect or can not be inspected and inputs an output signal to the scan flip-flop dedicated to observation, wherein the combinational circuit includes one input signal. A design signal for facilitating inspection, characterized in that the output signal changes in accordance with the change of the test pattern. 2. The testability design method according to claim 1 , wherein said combinational circuit is composed of one or a plurality of exclusive OR (EXOR) gates connected in a tree shape.
A testability design method characterized by being an R-tree. 3. The testability designing method according to claim 1 , wherein the combination circuit changes an output signal according to a change of one input signal when the remaining input signal has a predetermined value. A design method for facilitating inspection characterized by the following. 4. An integrated circuit can be easily inspected for failure.
The first step in scan design, and observing and observing signals at locations that are difficult or impossible to inspect.
The measured signal is output from the scan flip-flop dedicated to observation.
A second step of adding an energizing observation circuit to said integrated circuit
And the output signal of the observation circuit is configured in the first step.
Can be output from the integrated circuit via the configured scan chain
Scan flip-flop for observation only
And a third step of inserting
In addition, the inspection-easy designing method is characterized in that the difficult-to-inspection portion is a data input line of a tri-state element which does not output input data and is turned off when an integrated circuit is inspected. 5. The integrated circuit can be easily inspected for failure.
The first step in scan design, and observing and observing signals at locations that are difficult or impossible to inspect.
The measured signal is output from the scan flip-flop dedicated to observation.
A second step of adding an energizing observation circuit to said integrated circuit
And the output signal of the observation circuit is configured in the first step.
Can be output from the integrated circuit via the configured scan chain
Scan flip-flop for observation only
And a third step of inserting
For example, the first step is to configure multiple scan chains in an integrated circuit, the third step, so that the maximum number of scan flip-flops included in the scan chain is not increased,
A design method for facilitating inspection, wherein a scan flip-flop dedicated for observation is inserted. 6. The integrated circuit can be easily inspected for failure.
The first step in scan design, and observing and observing signals at locations that are difficult or impossible to inspect.
The measured signal is output from the scan flip-flop dedicated to observation.
A second step of adding an energizing observation circuit to said integrated circuit
And the output signal of the observation circuit is configured in the first step.
Can be output from the integrated circuit via the configured scan chain
Scan flip-flop for observation only
And a third step of inserting
For example, the first step is to configure multiple scan chains in an integrated circuit, the third step, as the number of scan flip-flops included in the scan chain is equalized, the observation dedicated scan flip A test design method for facilitating inspection, characterized in that the test is inserted. 7. An observation-only scan , which is an integrated circuit designed for scanning and operates only when the integrated circuit is inspected.
A scan chain including flip-flops is configured
In the integrated circuit, the observation-dedicated scan flip-flop uses, as a normal data input, a data input signal of a tri-state element which does not output input data and is turned off when an integrated circuit is inspected. 8. An observation-only scan , which is an integrated circuit designed for scanning and operates only when inspecting the integrated circuit.
A scan chain including flip-flops is configured
The scan flip-flop dedicated for observation has multiple inputs 1
An integrated circuit, which is an output and receives, as an input, an output signal of a combinational circuit whose output signal changes according to a change of one input signal. 9. An integrated circuit according to claim 8 , wherein said combinational circuit is comprised of one or a plurality of exclusive-OR (EXOR) gates connected in a tree shape.
An integrated circuit characterized by being an R-tree. 10. The integrated circuit according to claim 8 , wherein said combinational circuit is configured such that when the remaining input signal has a predetermined value, the output signal changes according to a change of one input signal. Integrated circuit characterized. 11. The integrated circuit according to claim 8 , wherein said combination circuit receives an enable input signal of a tri-state element as an input. 12. The integrated circuit according to claim 8 , wherein the combinational circuit receives a data input signal of a tri-state element which does not output input data and goes into an off state when testing the integrated circuit. An integrated circuit characterized by the above. 13. For a scan-designed integrated circuit,
A bus error avoidance design method for making a design change so that a bus error does not occur, comprising: determining whether an enable input of a tristate element included in the integrated circuit is controlled by a scan flip-flop; and A first process for extracting a bus connected to the data output terminals of the plurality of tri-state elements whose enable inputs are controlled by the scan flip-flop; and a data output terminal connected to the bus extracted in the first process. The output data of the scan flip-flop for controlling the enable input of the plurality of tri-state elements is input to the plurality of tri-state elements, and only one of the plurality of tri-state elements is used for testing the integrated circuit. Turns on to output through input data. A second process for generating a selection circuit for controlling enable inputs of the plurality of tri-state elements; and arranging the selection circuit generated in the second process in the integrated circuit, and an output terminal of the arranged selection circuit. And a third circuit for connecting to the enable input terminals of the plurality of tri-state elements, wherein the selection circuit generated in the second processing includes a scan flip-flop for controlling an enable input of the plurality of tri-state elements. A bus error avoiding design method characterized in that normal output data and inverted output data are input. 14. An integrated circuit which is scan-designed and redesigned so as not to cause a bus error, wherein a scan flip-flop is provided for a plurality of tri-state elements whose data output terminals are connected to a common bus. Controlling the enable input of the plurality of tri-state elements so that when the integrated circuit is inspected, only one of the plurality of tri-state elements passes through the input data and outputs the input data when testing the integrated circuit. An integrated circuit, wherein a selection circuit is provided, wherein the selection circuit receives normal output data and inverted output data of the scan flip-flop as inputs.