JPS645461B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an integrated circuit (hereinafter referred to as an IC) having a test circuit for logic operation functions, etc., and in particular to an output DC test for measuring leakage current and output current of an output terminal of an IC. This makes it easy and efficient to do so.

In recent years, ICs have become more integrated and larger, and along with this, testing methods to determine whether a completed IC is a good product or a defective product are becoming increasingly important. Traditionally, testing methods for such ICs include implementation testing, comparison testing, and IC testing.
There are methods such as using a tester, but it has the disadvantage that it is impossible to find defective parts in mounting tests, and a good sample for comparison is required in comparison tests.
Recently, although expensive, IC testers have been attracting attention because they are capable of detecting defective parts on a gate-by-gate basis and are highly versatile. IC testers also perform DC tests that measure leakage current and input or output current at the input and output terminals of the device under test, AC tests that measure rise and fall times and propagation delay times, and the functions of each block. Since it is possible to perform all types of tests, including functional tests, an increasing number of recent ICs incorporate test circuits that can be easily tested with an IC tester from the circuit design stage. This is extremely effective in evaluating engineering samples and determining pass/fail during mass production. However, on the other hand, since the tester is highly versatile, there is also the problem that a test program must be created for each product to be tested.
In particular, functional tests are completely different for each variety, so the current situation is that they require a great deal of effort to develop. At the same time, the output DC test, which measures the leakage current and output current of the output terminal by setting the logic level of the output terminal to H or L, also uses part of the functional test program mentioned above to set the logic level of the output terminal to H or L. Since it is set to L, the output
In order to perform the DC test, a functional test program was required, and there was a contradiction in that the output DC test, which should have been performed before the functional test, was postponed.

The present invention is designed to eliminate such drawbacks of the conventional example, and embodiments thereof will be described below with reference to the drawings.

The drawings show the internal blocks, pins, and wiring relationships of the IC according to the present invention. In the figure, during normal operation, a signal applied from pin 1, which is an external terminal, is applied to the circuit under test block 16 through the input buffer 8 so as to perform, for example, arithmetic processing, and the processing result is output as an output signal. The signal is applied to output buffers 12, 13, and 14 through output signal switching circuits 17, 18, and 19, and outputted through pins 5, 6, and 7, which are external terminals. in this case,
External terminals pins 2 and 3 and input buffer 9,
It is assumed that control signals A and B applied to the test mode decoding circuit 15 by 10 are both at L level.

Now, when performing an output DC test to measure the leakage current and output current of the output terminal, change the logic level of the signals applied to pins 2 and 3 to set the output signal E of the test mode decoding circuit 15 to H level, and A signal having the same logic level as the signal applied to pin 4, which is an external terminal, is output to terminals 5, 6, and 7. By doing this, the logic levels of pins 5, 6, and 7, which are output terminals, can be controlled only by the input signal from pin 4, so the DC test of the output terminals, that is, the output DC test, can be performed very easily. It's easy to do. Functional tests other than the DC test are performed by using a combination of logic levels of the signals applied to pins 2 and 3 other than the DC test, and by setting the output signal C or D of the test mode decoding circuit 15 to H. . In this embodiment, the test mode control signal is 2 bits A and B, but if it is 3 bits, it can control 9 modes, and if it is 4 bits, it can control 16 modes. In the illustrated embodiment, the logic level during the output DC test is input from the dedicated pin 4, but this may also be used as the input pin during the normal operation mode.

As described above, the IC of the present invention can directly and instantaneously control the logic level of the output signal at the output terminal with the signal applied to the input terminal during DC testing, so it can be used for evaluation of engineering samples or during mass production. The time required for determining whether the product is good or bad can be shortened and costs can be reduced, which is an extremely excellent effect.

[Brief explanation of the drawing]

The drawing is a main circuit block diagram of an embodiment of the present invention. 1-7...Pin, 8-11...Input buffer circuit, 12-14...Output buffer circuit, 15...
Test mode decoding circuit, 17-19...output signal switching circuit.

Claims (1)

[Claims] 1 Operation of an integrated circuit having means for functional operation testing and a circuit block under test, in which only one of a plurality of operation modes can be specified by inputting control signals from a plurality of external input terminals. A mode switching means, an output buffer means for outputting signals from each of the plurality of output external terminals, an output signal switching means connected to each of the output buffer means, and a signal input from the input external terminal. The output signal switching means includes an output signal from the circuit block under test, an output signal from the input buffer means, and one of the two output signals to the output signal. A signal for controlling switching so that the signal switching means selectively outputs is input from the operation mode switching means, and in a specific operation mode, the output can be changed by changing the logic level of the signal applied to the external input terminal. An integrated circuit characterized in that the logic level of an output signal from an external terminal can be controlled.