JPS60150662A - Semiconductor integrated logic device - Google Patents

Abstract

PURPOSE:To simplify the control of input-output cells, to reduce man-hours for preparing a pattern and to shorten testing time by adopting constitution separately mounted to an internal logic as an input-output cell control function. CONSTITUTION:An input-output cell control cell is connected to one or more of input-output cells 2 on the outside of a region containing a logic circuit, and controls the state of the input-output cells 2. When the input-output cells 2 are tested, the input-output cells 2 can be set to a desired state by bringing a terminal S to a ''1'' level and a terminal D1 to a ''0'' level and bringing a terminal D0 to a ''0'' or ''1'' level. Methods in which the structure, number and arrangement of the input-output cell control cells 3 and the ways of connection to the input- output cells 2 are arbitrary are adopted except a method in which one input- output cell control cell 3 is disposed at the center of an upper side and connected to all input-output cells 2. Input data to the input-output cell control cell 3 may be inputted through an internal logic circuit except direct input from a package pin.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to the configuration of an input/output circuit section of a semiconductor integrated logic device.

[Background of the invention]

FIG. 1 shows the configuration of an input/output circuit section of a semiconductor integrated logic device according to the prior art. 1 is an integrated circuit chip, and 2 is an input/output cell. Input/output cells are placed on each side of the chip.

FIG. 2 is an example of the human output cell in FIG. 1.

In such conventional technology, in order to measure the DC characteristics of the human output cell, the input/output cell "1" or NO+1 is
In order to set the state, it is necessary to set the state of the internal logic circuit and the pattern sequence given to the package bin so that the input/output cells are in the desired state. However, with this method, the logic scale included in chips has rapidly increased and become more complex due to recent advances in semiconductor technology.
It is expected that the number of man-hours required for pattern creation will increase, and the test time will also become longer.

[Purpose of the invention]

The object of the present invention is to eliminate the above-mentioned drawbacks of the prior art, and to be almost unaffected by an increase in logic scale.

The purpose is to provide an input/output circuit configuration that requires less man-hours for pattern creation.

[Key points of invention]

In a semiconductor integrated logic device, the input/output circuit section is generally located outside the area containing the logic circuit cells, in an area exclusively for human output, or these human output cells are generally located outside the area containing the logic circuit cells, or these human output cells are located outside the area containing the logic circuit cells. controlled only by Therefore, an internal logic circuit must be used to set the human output cell.

In the present invention, a function for controlling the state of the input/output cells for measuring the characteristics of the input/output circuits is arranged in the area where the input/output cells are located. This allows the state of the input/output cells to be controlled to 1' through a complex internal logic circuit, making the pattern M-shaped, reducing the number of man-hours required for pattern creation, and reducing the test time to 5! d can be reduced.

[Embodiments of the invention]

FIG. 6 shows an example of the configuration of the input/output circuit section according to the present invention. show.

3 is a human output cell city 1''1 wholesale cell which has the function of controlling input/output cells.

FIG. 4 shows an example Y of the input/output cell and input/output cell control cell in FIG. 6. 4 is a selector, which is provided to select from either the internal data Y1 to be sent to the input/output cell or the input/output cell control cell.

The input/output cell isolation 1 cell 3 is connected to one or more input/output cells 2 outside the area including the logic circuit and controls the state of the coarse output cell. In FIG. 4, it is connected to all input/output cells 2.

In the embodiment shown in FIG. 4, when testing input/output cells, the terminal S? :By setting the terminal DMY to the ``0'' level and setting the terminal DO to the 0'' or +1'' level, the input/output cell can be easily set to the right-hand state.

In this embodiment, one input/output cell control cell is placed at the center of the upper side and connected to all input/output cells. 2 can be connected in any way. An input/output cell control cell may be provided for each valley.

Further, in the embodiment, the input data of the input/output cell control cell is input directly from the package bin, but it may also be input through an internal logic circuit.

Further, in FIG. 4, a selector is provided at the input section of the input/output cell 20 to switch input data, but any selector may be used as long as it performs the same function for the input/output cell. Furthermore, it is also conceivable to provide this data switching function not in the input/output cell but in the input/output cell control cell.

In this way, 1 input/output cell t+'Q? , the internal principle is that by adopting a separate configuration, control of input/output cells becomes easier, pattern creation work is reduced,
Test special 1 can be shortened.

〔Effect of the invention] The present invention has the following effects.

(11 control becomes simple and the number of patterns decreases.

(2) The number of man-hours required for pattern creation is reduced.

(3) Test time is short.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional semiconductor integrated logic device, FIG. 2 is a circuit diagram of an input/output cell in FIG. 1, and FIG. 3 is an embodiment of a semiconductor integrated logic device according to the present invention. The configuration diagram, FIG. 4, is a circuit diagram of the human output cell and the input/output cell control cell in FIG. 3. 1...Integrated circuit chip 2...Input/output cell 6...Input/output control cell 4...Selector jf, r Diagram 2 Figure east 3 Line 4 rfJ

Claims (1)

[Claims] In a semiconductor integrated logic device that has an area dedicated to the input/output device 14F element outside the area where the logic elements are arranged, an element with a function of controlling the input/output functional element χ is also placed in the area dedicated to the input/output functional element. A semiconductor integrated logic device having a distribution If t% characteristic.