JPH03185756A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPH03185756A JPH03185756A JP1326274A JP32627489A JPH03185756A JP H03185756 A JPH03185756 A JP H03185756A JP 1326274 A JP1326274 A JP 1326274A JP 32627489 A JP32627489 A JP 32627489A JP H03185756 A JPH03185756 A JP H03185756A
- Authority
- JP
- Japan
- Prior art keywords
- internal logic
- output
- logic circuit
- circuit section
- input signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 4
- 238000012360 testing method Methods 0.000 claims abstract description 24
- 230000005540 biological transmission Effects 0.000 claims abstract description 14
- 238000011990 functional testing Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
- 230000000644 propagated effect Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
Landscapes
- Tests Of Electronic Circuits (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は半導体集積回路装置（以下ＬＳＩと略称する
）テスト時における出力電圧・電流特性テストを容易に
したＬＳＩに関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an LSI that facilitates testing of output voltage and current characteristics during testing of semiconductor integrated circuit devices (hereinafter abbreviated as LSI).
第２図は従来（７’）ＬＳＩＩ７’）ブロック回路図で
ある。FIG. 2 is a conventional (7') LSII7' block circuit diagram.
図において（１）は内部論理回路部に対する入力信号、
（２）は内部論理回路部、（８）は出力回路部、（９）
は外部出力端子である。In the figure, (1) is an input signal to the internal logic circuit section;
(2) is the internal logic circuit section, (8) is the output circuit section, (9)
is an external output terminal.
次に動作について説明する。入力信号（ＩＪに対応して
内部論理回路部（２１が動作し、その出力信号が出力回
路部（８）を介して外部出力端子（９）に伝搬される。Next, the operation will be explained. The internal logic circuit section (21) operates in response to the input signal (IJ), and its output signal is propagated to the external output terminal (9) via the output circuit section (8).
従来のＬＳＩは以上のように構成されているので、外部
出力端子の信号状態は、内部論理回路部の論理内容およ
び入力信号により決定されていた。Since the conventional LSI is configured as described above, the signal state of the external output terminal is determined by the logic content of the internal logic circuit section and the input signal.
したがって、出力電圧・電流特性をテストするたいには
、入力信号により内部論理回路部を所望の状態になるま
で動作させる必要がある。この際、論理内容によっては
各外部出力端子毎に内部論理回路部を動作させ状態設定
する必要があり、才だ論理回路の複雑化、高集積化に伴
うテスト入カバターンの長大化、ＬＳＩの多ピン化によ
り出力電圧・電流特性のテスト時間が増加するという問
題点があった。Therefore, in order to test the output voltage/current characteristics, it is necessary to operate the internal logic circuit section using an input signal until it reaches a desired state. At this time, depending on the logic content, it is necessary to operate the internal logic circuit section for each external output terminal to set the state. There was a problem in that the test time for output voltage and current characteristics increased due to the use of pins.
この発明は上記のような問題点を解消するた力になされ
たもので、出力電圧・電流特性のテストを容易化できる
ＬＳＩを得ることを目的とする。The present invention was made to solve the above-mentioned problems, and an object of the present invention is to obtain an LSI that can facilitate testing of output voltage and current characteristics.
この発明に係るＬＳＩは内部論理回路部と出力回路部ｎ
ｆ９ｊ５に内部論理回路部からの出力信号とテスト入力
信号を選択するた力のトランスミッシ。The LSI according to the present invention has an internal logic circuit section and an output circuit section n.
F9J5 is a power transmission for selecting the output signal from the internal logic circuit section and the test input signal.
ンゲートを設けたものである。It is equipped with a link gate.
この発明におけるトランスミッションゲートは制御信号
により実使用時育たば機能テスト時１．を内部論理回路
部からの出力信号を出力回路部に伝搬し、出力電圧・電
流特性テスト時はテスト入力信号を出力回路部に伝搬す
る。The transmission gate in this invention is controlled by a control signal during actual use and during a function test.1. The output signal from the internal logic circuit section is propagated to the output circuit section, and the test input signal is propagated to the output circuit section when testing the output voltage/current characteristics.
以下、この発明の一実施例を図について説明する。第１
図はＬＳＩのブロック回路図である。図において（１）
、（２１、（８）、（９）は第２図の従来例に示しｔコ
ものど同等でゐるので説明を省略する。（３）はテスト
制御入力信号、（４）はテストデータ入力信号、（５）
はインバータ、＜６１ 、 （７１はトランスミッショ
ンゲート、である。An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure is a block circuit diagram of an LSI. In the figure (1)
, (21, (8), and (9) are shown in the conventional example in Fig. 2, and the explanation thereof will be omitted since they are all the same. (3) is a test control input signal, and (4) is a test data input signal. ,(5)
is an inverter, <61, (71 is a transmission gate).
次に動作について説明する。入力信号（１）に対応して
内部論理回路部（２）が動作し、テスト制御入力信号（
３）が電源レベル（以下Ｈと略称する）０場合トランス
ミッションゲート（６）が導通状態、トランスミッショ
ンゲート（７）が非導通状態となり、内部論理回路部（
２）の出力信号がトランスミッションゲート（６）およ
び出力回路部（８）を介して外部出力端子（９）に伝搬
する。一方、テスト制御入力信号（３）が接地レベル（
以下りと略称する）の場合、トランスミッションゲート
（６）が非導通状態、トランスミッションゲート（７）
が導通状態となりテストデータ入力信号り４）が、トラ
ンスミッションゲート（７）および出力回路部（８）を
介して外部出力端子（９）に伝搬する。Next, the operation will be explained. The internal logic circuit section (2) operates in response to the input signal (1), and the test control input signal (
3) when the power supply level (hereinafter abbreviated as H) is 0, the transmission gate (6) becomes conductive, the transmission gate (7) becomes non-conductive, and the internal logic circuit section (
The output signal of 2) is propagated to the external output terminal (9) via the transmission gate (6) and the output circuit section (8). On the other hand, the test control input signal (3) is at ground level (
), the transmission gate (6) is in a non-conducting state, and the transmission gate (7) is in a non-conducting state.
becomes conductive, and the test data input signal 4) is propagated to the external output terminal (9) via the transmission gate (7) and the output circuit section (8).
したがって、実使用時または機能テスト時はテスト制御
入力信号（３）をＨにしておけば、内部論理回路部（２
）の出力信号が外部出力端子（９）に伝搬され、通常ｆ
ｌＬｓＩとしての機能を満たし、出力電圧・電流特性テ
スト時にはテスト制御入力信号（３）をＬにしておけば
、テストデータ入力信号（４１が外部出力端子（９）に
伝搬されるので、内部論理回路部（２１の論理内容およ
び入力信号（１）に係りなく外部出力端子（９）の状態
設定ができる。Therefore, during actual use or functional testing, if the test control input signal (3) is set to H, the internal logic circuit section (2
) is propagated to the external output terminal (9), and normally f
If the function as lLsI is satisfied and the test control input signal (3) is set to L when testing the output voltage/current characteristics, the test data input signal (41) is propagated to the external output terminal (9), so the internal logic circuit The state of the external output terminal (9) can be set regardless of the logic contents of the section (21) and the input signal (1).
以上のように、この発明によれば入カバターンを印加す
ることなく直接出力回路部を制御し、出力電圧・電流特
性をテストできるという効果がある。As described above, according to the present invention, the output circuit section can be directly controlled without applying an input voltage, and the output voltage/current characteristics can be tested.
第１図はこの発明の一実施例であるＬＳＩのブロック回
路図、第２図は従来のＬＳＩのブロック回路図である。
図において、（１）は入力信号、（２）は内部論理回路
部、（３）はテスト制御入力信号、（４）はテストデー
タ入力信号、（５）はインバータ、（６）（７）はトラ
ンスミッションゲート、（８）は出力回路部、（９）は
外部出力端子を示す。
なお、図中、同一符号は同一、または相当部分を示す。FIG. 1 is a block circuit diagram of an LSI according to an embodiment of the present invention, and FIG. 2 is a block circuit diagram of a conventional LSI. In the figure, (1) is an input signal, (2) is an internal logic circuit, (3) is a test control input signal, (4) is a test data input signal, (5) is an inverter, and (6) and (7) are The transmission gate, (8) is an output circuit section, and (9) is an external output terminal. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.
Claims (1)
路装置において、内部論理回路部と出力回路部の間に内
部論理回路部からの出力信号とテスト入力信号を選択す
るトランスミッションゲート部を具備したことを特徴と
する半導体集積回路装置。In a semiconductor integrated circuit device having an input/output circuit and an internal logic circuit section, a transmission gate section for selecting an output signal from the internal logic circuit section and a test input signal is provided between the internal logic circuit section and the output circuit section. A semiconductor integrated circuit device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1326274A JPH03185756A (en) | 1989-12-14 | 1989-12-14 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1326274A JPH03185756A (en) | 1989-12-14 | 1989-12-14 | Semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03185756A true JPH03185756A (en) | 1991-08-13 |
Family
ID=18185936
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1326274A Pending JPH03185756A (en) | 1989-12-14 | 1989-12-14 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03185756A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6838891B2 (en) * | 2001-04-09 | 2005-01-04 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device |
-
1989
- 1989-12-14 JP JP1326274A patent/JPH03185756A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6838891B2 (en) * | 2001-04-09 | 2005-01-04 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device |
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