JPH05264647A - Test circuit for semiconductor device - Google Patents

Abstract

PURPOSE:To facilitate the measurement of input and output characteristics of a semiconductor device and perform the measurement within a short time. CONSTITUTION:A test device for semiconductor device has a multiplexer 12 for distributing a plurality of inputs according to the number of input terminals and a multiplexer 14 for switching the output of the multiplexer 12 and the output signal at general operation according to the number of output terminals. The circuit for distributing the inputs is switched by a common control circuit 11, and the circuit for switching the output signals is switched by a common switch signal 15, whereby the input and output characteristics can be simultaneously measured.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device test circuit, and more particularly to a test circuit for measuring electrical characteristics of input / output terminals.

[0002]

2. Description of the Related Art In a conventional semiconductor device, a test pattern prepared in advance is used to measure an input voltage characteristic of an input terminal and an output voltage characteristic of an output terminal,
After setting the input conditions and output judgment conditions in the test program, run the test program on the LSI tester and measure. Specifically, in the case of the input characteristics, after setting the input conditions such as the input voltage and the operating frequency defined by the standard in the test program, the function test is performed and the pass / fail judgment is made by whether or not the test passes. ..

Also, when measuring the output voltage characteristic, as in the case of the input voltage characteristic, it is confirmed that the function test has passed, and then when the output current is measured, a predetermined voltage is applied to the output terminal. Is applied and the current flowing at that time is measured.

Further, when measuring the output voltage, a predetermined current is made to flow from the output terminal or is made to flow to the output terminal, and the voltage generated at the output terminal at that time is measured.

[0005]

According to the conventional method, not only the test program but also the test pattern is required to measure the input / output voltage characteristics. However, since the test pattern is created even in the function test, the test pattern for the input / output voltage characteristic is not created.
Normally, it also serves as a test pattern for a function test. Therefore, the measurement terminals are not measured at once, and the “pattern check” and “input / output voltage measurement” are repeated for each pin to be measured, which is inefficient and the longer the measurement time, the longer the measurement terminals. There was a problem.

An object of the present invention is to solve the above-mentioned problems and to provide a test circuit for a semiconductor device which enables efficient testing in a short time.

[0007]

According to the structure of a test circuit of a semiconductor device of the present invention, a first multiplexer for selecting a signal respectively inputted from a plurality of input terminals, and the first multiplexer are controlled. A control circuit and a second multiplexer for switching between the output of the first multiplexer and a signal to be originally output to the output terminal of the semiconductor device are provided, and in particular, the second multiplexer is provided according to the total number of the input terminals and the output terminals. The number of inputs of the first multiplexer is the same as or different from each other.

[0008]

1 is a block diagram showing a test circuit according to a first embodiment of the present invention. 1, in the present embodiment, the terminal 1 is connected to the input of the input buffer inverter 4, and the output of the input buffer inverter 4 is connected to the input of the input buffer inverter 5. The inverters 4 and 5 are buffers for supplying an input signal applied to the semiconductor device to a circuit in the semiconductor device, and are usually arranged near the input terminal 1.

The relationship between the input terminal 2, the inverter 7, the input terminal 3, the inverter 8 and the inverter 9 is the same. The outputs of the inverter 5, the inverter 7, and the inverter 9 are indicated by arrows. Each is connected to a predetermined circuit and is also connected to the 3-input multiplexer 12. The multiplexer 12 selects one of the three input signals according to the output of the control circuit 11,
The control circuit 11 can switch its output by a signal input to the control signal input terminal 10, and can return the control circuit 11 to an initial state by a signal input from a reset signal input terminal 19.

The output of the multiplexer 12 is connected to one input of a 2-input multiplexer 14. The multiplexer 14 switches its output according to the signal input to the switching signal input terminal 15 and transfers the signal to the input of the inverter 16. Inverter 16 and inverter 1
An output buffer 7 transfers a signal input to the output buffer 16 to an output terminal 18. The input terminal 13 is
This is an input terminal for a signal output to the output terminal 18 when the semiconductor device is in the normal mode.

FIG. 2 is a circuit diagram showing an example of the control circuit 11 shown in FIG. In FIG. 2, D flip-flop 2
1, 2, 23 have three stages, and each output Q is output to the multiplexer 12.

Here, it is assumed that a low voltage level (hereinafter abbreviated as "L") is once input to the input terminal 19 and thereafter a high voltage level (hereinafter abbreviated as "H") is maintained. The multiplexer 12 outputs the output of the inverter 5 when the outputs of the D flip-flops (hereinafter abbreviated as D / F / F) 21, 22, 23 in the control circuit 11 are "H", "L", and "L". , "L", "H", "L" outputs the output of the inverter 7, and "L", "L", "H" outputs the output of the inverter 9, respectively. Multiplexer 1
4 outputs the signal input to the input terminal 13 when the signal input to the switching signal input terminal 15 is “L” and the output of the multiplexer 12 when the signal is “H”.

First, the D / F / F 21, 2 of the control circuit 11
When the Q outputs 2 and 23 are "H", "L", and "L", the output of the multiplexer 12 transfers the output of the inverter 5 to one of the multiplexers 14. When the input of the switching signal input terminal 15 is set to “H”, the multiplexer 14 transfers the output of the multiplexer 12 to the inverter 16.
Therefore, at this time, the input applied to the input terminal 1 is output to the output terminal 18.

When one clock is input to the control signal input terminal 10 while the input terminal 15 is kept at "H", D.
The Q outputs of the F / Fs 21, 22 and 23 are "L",
Since it becomes “H” and “L”, the multiplexer 12 outputs the output of the inverter 7 to the multiplexer 14. Therefore, at this time, the input applied to the input terminal 2 is output to the output terminal 18.

When one clock is again input to the control signal input terminal 10 while the input terminal 15 is kept at "H",
Each output of the D / F / F 21, 22, 23 is “L”,
Since it becomes “L” and “H”, the multiplexer 12 outputs the output of the inverter 9 to the multiplexer 14. Therefore, at this time, the input applied to the input terminal 3 is output to the output terminal 18.

When the input of the input terminal 15 is set to "L", the multiplexer 14 selects the signal input to the input terminal 13. Therefore, at this time, the output of the control circuit 11, that is, D · F.
The input of the input terminal 13 is output to the output terminal 18 regardless of the Q outputs of the / F 21, 22, and 23.

FIG. 3 is a block diagram of the second embodiment of the present invention. In FIG. 3, the present embodiment is almost the same as FIG. 1, except for the following points.

The number of input terminals 24 and 25 is only two in total, and the output Q of the control circuit 11 may be two wirings. Other parts are the same as in FIG.

FIG. 4 is a block diagram showing a test circuit of a semiconductor device according to the third embodiment of the present invention.

Referring to FIG. 4, this embodiment shows the input terminals 1,
2, 3, 24, 25 and output terminals 18, 35, 40,
Control signal input terminal 10 and reset signal input terminal 19
, Control circuit 11, and multiplexers 12, 14, 3
0, 37 and inverters 4-9, 16, 17, 26-2
9, 33, 34, 38, 39, semiconductor device output input terminals 13, 31, 36, and switching signal input terminal 15.

In this embodiment, when "H" is applied to the input terminal 15, the D / F / F 21, 22, 23 in the control circuit 11 are operated.
When the Q output is "H", "L", "L", the signal input to the input terminal 1 is output terminal 18, and the signal input to the input terminal 24 is output terminal 35 and output terminal 40. It is output respectively. In addition, D / F / F21,22,23
When the Q output of is "L", "H", "L", input terminal 2
The signal input to the output terminal 18 and the input terminal 25
To the output terminal 35 and the output terminal 40, respectively. The Q output of the D / F / F21 to 23 is output as "L", but the output terminals 35 and 40
Nothing is output to. When "L" is applied to the input terminal 15, the signals output in the normal mode are output to the output terminals 18, 35 and 40.

As described above, a plurality of multiplexers having different numbers of inputs depending on the number of input terminals and output terminals are combined, and when the number of output terminals is larger than the number of input terminals, they are shared. Easy to configure.

[0023]

As described above, according to the present invention, since the input signals of a plurality of input terminals can be switched to the output terminal and output, the input voltage characteristics of the plurality of input terminals can be easily measured and the There is an effect that the input voltage characteristic of the semiconductor device having different numbers of outputs can be measured in a shorter time than before, and the test program can be easily created and debugged.

[Brief description of drawings]

FIG. 1 is a block diagram showing a test circuit of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a control circuit shown in FIG.

FIG. 3 is a block diagram showing a second embodiment of the present invention.

FIG. 4 is a block diagram showing a third embodiment of the present invention.

[Explanation of symbols]

1-3, 24, 25 input terminals 4-9, 16, 17, 26-29, 33, 34, 38,
39 Inverter 10 Control signal input terminal 11 Control circuit 12, 14, 30, 32, 37 Multiplexer 19 Reset signal input terminal 13, 31, 36 Input terminal of semiconductor device output 18, 35, 40 Output terminal 21-23 D flip-flop 15 Switching signal input terminal

Claims (4)

[Claims] 1. A first multiplexer for selecting one signal from signals applied to each of a plurality of input terminals, and a control circuit for controlling the first multiplexer.
A test circuit for a semiconductor device, comprising: a second multiplexer that switches between a signal selected by the control circuit and another signal and outputs the signal to an output terminal. 2. The test circuit for a semiconductor device according to claim 1, wherein a plurality of the first multiplexers are prepared according to the total number of the input terminals and the output terminals. 3. The test circuit for a semiconductor device according to claim 1, wherein the plurality of first multiplexers have the same number of inputs or different numbers of inputs. 4. The test circuit for a semiconductor device according to claim 1, wherein a plurality of second multiplexers are prepared.