JPH05113469A - Semiconductor device - Google Patents

Abstract

PURPOSE:To make the functional test of a circuit block further than an internal bus easy by providing a control means and by carrying out the state setting of the bus directly from the outside. CONSTITUTION:Switches 15, 16 are provided to be controlled so that output signals of circuit blocks 20, 21 do not compete each other in an internal bus 7. Usually, switches 15, 16 are controlled by the signals of terminals 2, 4, the state of the bus is set by the result of operations of the circuit blocks 20, 21 by signals inputted by terminals 22, and a circuit block 24 is operated. Further, a switch 17 operated in inputting a signal direct from an external terminal to the bus is set up and controlled by a control terminal 6. In inputting the signal direct from the input terminal 5 to the bus 7, the switch 17 becomes on, and switches 15, 16 compulsorily become of then. Namely, the state of the bus is set by the signal inputted from the terminal 5, and the block 24 is operated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus circuit of a semiconductor device.

[0002]

2. Description of the Related Art A conventional technique will be described with reference to an example of a bus circuit using MOS transistors. A conventional bus circuit is shown in FIG. The plurality of output signals of the circuit block 320 are connected to the internal bus 307, and the internal bus 307 is connected to the input terminal of the circuit block 330 to form a bus circuit.
Reference numeral 322 is a terminal for inputting a signal to the semiconductor device from the outside, and reference numeral 323 is a terminal for taking a signal from the semiconductor device to the outside.

A tri-state gate is usually used as an output terminal of a circuit block connected to a bus. In FIG. 4, 310 and 311 are tristate gates. Tri-state gates 310 and 311 in the circuit block 320
The terminals 301, 302, 303, 304 of are internal nodes in the semiconductor device, and the state of these terminals is the terminal 32.
The signal input to 2 is determined as a result of passing through a plurality of stages of logic gates. The signal input to the terminal 301 is controlled by the signal input to the terminal 302 and output to the internal bus 307. When a LOW level (hereinafter simply referred to as an L level) is input to the terminal 302, the terminal 3
The normal signal of the signal input to 01 is output to the internal bus 307. Conversely, when a HIGH level (hereinafter simply referred to as H level) is input to the terminal 302, the tristate gate 310 is in a high impedance state (hereinafter simply referred to as HZ).
The signal input to the terminal 301 is not transmitted to the internal bus 307.

In the internal bus to which a plurality of tristate gates are connected as shown in FIG. 4, one of the tristate gates is set to the active state, and the other tristate gates are set to the HZ state. It is generally controlled and used so that signals do not conflict on the internal bus.

In the functional test of the semiconductor device, a signal is input from the outside to verify whether the circuit is operating normally. As shown in FIG. 4, the circuit block 32 is divided by function with the internal bus as a boundary.
Even if the circuit blocks are divided into 0 and 330, it is impossible to individually perform a functional test on each circuit block. For example, when performing a functional test on the circuit block 330, the purpose is to use the internal bus 307. It is necessary to set to the state. Usually, the terminals 301 to 304 are internal nodes in the semiconductor device, and in order to set the states required for these terminals, it is necessary to trace the logic gates of a plurality of stages back to the terminal 322 and set the states. . The number of man-hours required to set this state becomes more difficult as the circuit contents become more complicated, making the function test even more difficult.

[0006]

SUMMARY OF THE INVENTION Therefore, the present invention is to solve such a problem, and an object of the present invention is to enable a state setting of an internal bus directly from the outside in a semiconductor device having an internal bus. It is an object to supply a semiconductor device that enables a functional test of circuit blocks after the internal bus without considering the state setting of the circuit blocks in the preceding stage of the bus.

[0007]

A semiconductor device using a MOS transistor is provided with a means for controlling a signal of an internal bus from the outside.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The semiconductor device of the present invention will be described in detail based on an embodiment using a MOS transistor.

The semiconductor device of the present invention basically has the structure shown in FIG. In FIG. 1, broken lines 20 and 21 are circuit blocks connected to the internal bus 7. The output terminals of the circuit blocks are controlled so that the output signals of the circuit blocks do not conflict with each other on the internal bus. Switch 15,
16 are prepared. The switches 15 and 16 are controlled by the terminals 2 and 4. For example, when the signal of the terminal 1 is transmitted to the terminal 13, the switch 16 is turned off and the signal of the terminal 3 is controlled not to be transmitted to the terminal 14. However, signals do not compete on the internal bus 7.
Note that terminals 1, 2, 3, and 4 are names given for convenience, and signals of internal nodes in these circuit blocks are signals given to an input terminal 22 for inputting signals from outside the semiconductor device. Is determined as a result of passing through the internal circuits 31 and 32. 10 and 11 are switches 15 and 16
Which is a signal selecting means for controlling the
The signals 5 and 16 are controlled by the signals 2 and 4, and the state of the internal bus is set by the result of the operation of the circuit blocks 20 and 21 by the signal input from the terminal 22, and the circuit block 24 operates. The switch 17 is a switch that operates when a signal is directly input to the internal bus from an external terminal, and is in an OFF state when the switches 15 and 16 are controlled by the signals 2 and 4. The switch 17 is controlled by the control terminal 6, and is turned on when a signal is directly input to the internal bus 7 from the input terminal 5, and at that time, the switches 15 and 16 are irrespective of the signal states of the terminals 2 and 4. It is forcibly turned off. That is, the state of the internal bus 7 is set by the signal input from the terminal 5, and the circuit block 24 operates.

Next, the operation of the present invention will be described using an actual circuit. In FIG. 2, a broken line 120 is a circuit block connected to the internal bus, and tri-state gates 110 and 111 are prepared at the output terminals of this circuit block. A broken line 130 is a circuit block operated by a signal of the internal bus. The dashed-dotted line 100 is a means for controlling the signal of the internal bus. The terminal 122 is a terminal for inputting a signal to the semiconductor device from the outside, and the circuit block 120 normally operates according to the signal input from the terminal 122. Terminals 101, 102, 103, 1 of tristate gates 110, 111 in the circuit block 120
Reference numeral 04 is an internal node in the semiconductor device, and the states of these terminals are set as a result of the signal input to the terminal 122 passing through a plurality of stages of logic gates.

The operation of the control means 100 will be described.
The tri-state gate 112 is used when controlling the signal on the internal bus from the outside. The terminal 105 is used to externally set the state of the internal bus, and the terminal 106 sets the signal input to the terminal 105 to the internal bus or the terminal 1
Circuit block 1 operated by the signal input from 22
It is a terminal for switching whether to set 20 output signals. When the L level is input to the terminal 106, the tristate gate 112 is in the active state, the tristate gates 110 and 111 are in the HZ state, and the signal input to the terminal 105 is set to the internal bus 107. In this case, the circuit block 130 operated by the signal of the internal bus is directly operated by the signal input to the terminal 105, and the result is the terminal 123 for extracting the signal from the semiconductor device.
Is output to. On the contrary, when the H level is input to the terminal 106, 112 enters the HZ state and the signal input to the terminal 105 is not output to the internal bus, and the internal signal is output as a result of the circuit block 120 operating according to the signal input from the terminal 122. The state of the bus is set, and the circuit block 130 has an original function of operating.

The above embodiment is merely one embodiment, and when the H level is input to the terminal 206 by configuring the control means as shown by the one-dot chain line 200 in FIG.
It is also possible to set the signal of the terminal 205 to the internal bus 207. Similar effects can be expected by using a tri-state gate having an inverted output as shown in FIG. Further, the method of constructing the logic circuit for controlling the tri-state gate is not particularly limited.

[0013]

As described above, according to the invention, the MOS
In the semiconductor device using the transistor, the state of the internal bus can be set directly from the outside of the semiconductor device by including the means for controlling the signal of the internal bus from the outside. This makes it possible to directly input signals from the outside to the circuit blocks after the internal bus, making it easy to test the function of the circuit blocks after the internal bus without considering the setting of the state of the circuit block at the previous stage of the internal bus. It is possible to do. This is effective in reducing the load of the functional test, which increases with the complexity of the semiconductor device.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of the present invention.

FIG. 2 is a configuration diagram showing an embodiment of the present invention.

FIG. 3 is a configuration diagram showing another embodiment of the present invention.

FIG. 4 is a configuration diagram showing a conventional embodiment.

FIG. 5 is a configuration diagram showing another embodiment of the present invention.

[Explanation of symbols]

 1 terminal (input, internal node) 2 terminal (control, internal node) 3 terminal (input, internal node) 4 terminal (control, internal node) 5 input terminal 6 control terminal 10 terminal (control, internal node) ) Control means 11 terminal (for control, internal node) control means 13 terminal (internal node) 14 terminal (internal node) 15 switch 16 switch 17 switch 20 circuit block 21 circuit block 22 input terminal 23 output terminal 24 circuit block 31 Internal circuit 32 Internal circuit 100 Control means 101 terminal (input, internal node) 102 terminal (control, internal node) 103 terminal (input, internal node) 104 terminal (control, internal node) 105 input terminal 106 control terminal 107 Internal Bus 108 Logic Gate 109 Logic Gate 110 Tristate Gate Gate 111 tri-state gate 112 tri-state gate 120 circuit block 122 input terminal 123 output terminal 130 circuit block 200 control means 201 terminal (input, internal node) 202 terminal (control, internal node) 203 terminal (input, internal) Node) 204 terminal (for control, internal node) 205 input terminal 206 control terminal 207 internal bus 208 logic gate 209 logic gate 210 tristate gate 211 tristate gate 212 tristate gate 213 logic gate 220 circuit block 222 input terminal 223 output terminal 230 circuit block 301 terminal (input, internal node) 302 terminal (control, internal node) 303 terminal (input, internal node) 304 terminal (control, internal node) 307 Internal bus 310 Tri-state gate 311 Tri-state gate 320 Circuit block 322 Input terminal 323 Output terminal 330 Circuit block 400 Control means 401 terminal (input, internal node) 402 terminal (control, internal node) 403 terminal (input, internal) Node) 404 terminal (for control, internal node) 405 input terminal 406 control terminal 407 internal bus 408 logic gate 409 logic gate 410 tri-state gate 411 tri-state gate 412 tri-state gate 420 circuit block 422 input terminal 423 output terminal 430 circuit block

Claims (1)

[Claims] 1. A semiconductor device using a metal oxide semiconductor (hereinafter simply referred to as a MOS transistor), which has means for externally controlling a signal of an internal bus.