JP2514989B2 - Sequential circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sequential circuit, and more particularly to a scan latch circuit for performing a scan test of a logic circuit in the sequential circuit.

[Conventional technology]

FIG. 3 is a block diagram of a conventional sequential circuit. In the figure, 1 is a scan register, 2 is a logic circuit, 3 is a selector circuit, and 4a and 4b are master latches and slave latches for performing data latching, respectively.

 Next, the operation will be described.

Scan register 1 when not used as a test circuit
Acts as a normal master-slave latch. At this time, the selector circuit 3 selects the input b or the input d by the select signal h. Here, the input b and the input d are respectively outputs of the logic circuit 2 in the preceding stage of each scan register 1. The signal selected by the selector circuit 3 is held by the master latch 4a and the slave latch 4b and sent to the logic circuit of the next stage. At this time, the master latch 4a and the slave latch 4b are gated by reciprocal or non-overlapping clocks f and g to form a sequential circuit together with a logic circuit.

On the other hand, when used as a test circuit, the scan register 1 functions as a shift register and a normal master / slave latch.

That is, first, in order to set the input of the logic circuit 2, the selector circuit 3 is caused to select the input a and the input c by the selector signal h. The input a is the output of the scan latch at the previous stage or a signal from the external input terminal, and the desired value (1 or 0) is set in the data latch circuits 4a and 4b by serially sending data by the clocks f and g.

Then, while the desired data is set in the data latch circuits 4a and 4b, the selector selection signal h is switched to cause the selector circuit 3 to select the input b and the input d. Since the input b and the input d are the outputs of the logic circuit 2 in the preceding stage of each selector circuit 3 as described above, the clocks f and g in this state.
Is input only once, the output of the logic circuit is set in the data latch circuits 4a and 4b. Here, the selector selection signal h is switched again, the selector circuit 3 is switched to the inputs a and c, and the value set in the data latch by the clocks f and g is serially sent to the terminal e. This terminal e is an input or output terminal of the scan register 1 in the subsequent stage.

Therefore, the control signal h of the selector circuit 3 and the clocks f and g
By switching between, it becomes possible to retrieve the input data set and output data to the logic circuit, and to test the logic circuit 2. Note that FIG. 5 shows a time chart of each signal related to these operations.

[Problems to be solved by the invention]

The conventional sequential circuit is configured as described above, and since a master-slave type scan register is required for the input section and the output section of the logic circuit, there is a problem that the number of elements in the entire circuit increases. there were.

In the sequential circuit shown in FIG. 4, some of the logic circuits 2a, 2a
There is only one data latch in the subsequent stage of b, and in such a structure, there is a problem that a data latch circuit must be added at the time of the scan test, and the number of elements greatly increases. .

The present invention has been made to solve the above problems, and does not require a master-slave type scan register in the input section and the output section of a logic circuit, thereby reducing the number of elements in the entire circuit. Aim to get the circuit.

[Means for solving problems]

In a sequential circuit in which a logic circuit and a scan latch circuit for performing a scan test of the logic circuit are alternately connected, the scan latch circuit is provided with either the output of the logic circuit at the preceding stage or the shift signal from the preceding stage. A single latch circuit of the scan latch circuit, which is composed of a selector circuit that selects one of the two and a single latch circuit that latches the selected output of the selector circuit, and that is connected to the input side of the logic circuit is A single latch circuit of the scan latch circuit connected to the output side of the logic circuit is either a latch circuit to be a master latch circuit or a latch circuit to be a slave latch circuit. , Or of the latch circuit that becomes the slave latch circuit, the scan latch circuit connected to the input side Of a single latch circuit is characterized in that it is a different one.

[Action]

According to the present invention, by adopting the above configuration, each selector circuit of the input side and output side scan latch circuits of the logic circuit independently performs input selection.
It is possible to switch between the sequential circuit operation at the normal time and the scan operation at the test time. As a result, the master-slave type scan register is not required, and the number of elements of the entire circuit can be reduced.

〔Example〕

 An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a sequential circuit according to an embodiment of the present invention.
1 to 1c are scan latches, each of which is an input selector circuit 3a
.About.3c and data latch circuits 4a to 4c.
Logic circuits 2a and 2b are inserted between the scan latches 1a and 1b and between the scan latches 1b and 1c.

 Next, the operation will be described.

Normally, the selectors 3a and 3b have the select selection signals ha and
The outputs b, d, j of the logic circuit are selected by hb, and in this state, the data latches 4a-4c are controlled by the two-phase non-overlapping clocks f and g to perform the sequential circuit operation.

On the other hand, during the test, the scan latch circuit functions as a shift register and a normal data latch as in the conventional one.

This operation will be described first in the case of testing the logic circuit 2a. A shift register is formed by selecting the signals a and c to the selector circuits 3a and 3b by the selector input selection signals ha and hb, and in this state, data is serially sent from the outside by the clocks f and g, thereby the data latch circuit. Set the desired value in 4a. This data latch circuit 4a
The output of is the input data of the logic circuit 2a. Here, in the state where the clock f is L, that is, in the state where the gate of the data latch 4a is not opened, only the selector selection signal hb is switched to make the selector circuit 3b select the input d side in the normal state, and the clock g is set to H in this state. That is, the gate of the data latch circuit 4b is opened and the output of the logic circuit 2a is latched.

After that, the selector selection signal hb is switched, the selector circuit 3b is made to select the input c side, and the shift register is constructed again. In this state, the data is shifted by the clocks f and g and the output of the logic circuit 2a is taken out.

Next, the test of the logic circuit 2b will be described. The selector selection signal configures a shift register in the same manner as in the test of the logic circuit 2a, and sets a desired value in the data latch circuit 4b. Here, when the clock g is in the L state, only the selector selection signal ha is switched to cause the selector circuit 3c to select the input j side at the normal time, and in this state, the clock f is set to H to output the output of the logic circuit 2b to the data latch circuit 4c. Make it latch. After this, similarly to the test of the logic circuit 2a, the output of the logic circuit 2b is taken out by the shift operation. The second
The figure shows a time chart when testing the logic circuits 2a and 2b.

As described above, in the present embodiment, instead of the master-slave type scan latch, the input selectors are provided independently for the master latch and the slave latch. Therefore, the elements are effectively used to reduce the number of elements. be able to.

Further, in the sequential circuit of this embodiment, when it is desired to have a configuration in which no logic circuit is inserted between the master latch and the slave latch like the conventional sequential circuit, a scan latch corresponding to the master latch and the slave latch, for example, a data latch. It is only necessary to switch the selector selection signals of the input selectors 3a and 3b of the circuits 4a and 4b at the same time. In this case, since the same operation as the conventional test circuit is performed, the conventional test method is also realized by the circuit configuration of this embodiment. it can.

Although the logic circuit is inserted between the scan latches corresponding to the master latch and the slave latch in the above-mentioned embodiment, there may be a portion where the logic circuit is not inserted, and the operation is not affected at all.

〔The invention's effect〕

As described above, according to the present invention, by making the selector circuits of the scan latch circuits on the input side and the output side of the logic circuit independently perform the input selection, the sequential circuit operation at the normal time and the scan operation at the test time can be performed. Since they can be switched, there is an effect that a master-slave type scan register is not required and a sequential circuit having a small number of elements in the entire circuit can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing a sequential circuit according to an embodiment of the present invention, FIG. 2 is a flow chart for explaining the operation of the sequential circuit during a logic circuit test, and FIG. 3 is a conventional sequential circuit. FIG. 4 is a block diagram showing the configuration of another conventional sequential circuit, and FIG. 5 is a flow chart for explaining the operation of the sequential circuit shown in FIG. 3 during a logic circuit test. 1a to 1c …… scan latch circuit, 2a, 2b …… logic circuit, 3
a-3c …… Selector, 4a-4c …… Data latch, ha, hb…
… Selector selection signal. The same reference numerals in the drawings indicate the same or corresponding parts.

Claims (2)

(57) [Claims] 1. In a sequential circuit in which a logic circuit and a scan latch circuit for performing a scan test of the logic circuit are alternately connected, the scan latch circuit is provided from the output of the logic circuit at the preceding stage or from the preceding stage. A selector circuit that selects one of the shift signals and a single latch circuit that latches the selected output of the selector circuit, and a single latch circuit of the scan latch circuit connected to the input side of the logic circuit. Of the scan latch circuit connected to the output side of the logic circuit is a master latch circuit. Of the latch circuit to be the circuit or the latch circuit to be the slave latch circuit, which is connected to the input side. Sequential circuit, characterized in that it is a different one than the single latch circuit Yanratchi circuit. 2. The selection control signals of the selector circuits of the scan latch circuits on the input side and the output side of the logic circuit are controlled independently of each other. Sequential circuit.