JPS63234553A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPS63234553A JPS63234553A JP6960287A JP6960287A JPS63234553A JP S63234553 A JPS63234553 A JP S63234553A JP 6960287 A JP6960287 A JP 6960287A JP 6960287 A JP6960287 A JP 6960287A JP S63234553 A JPS63234553 A JP S63234553A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- oscillation circuit
- oscillation
- circuit
- chips
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 230000010355 oscillation Effects 0.000 claims abstract description 36
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052782 aluminium Inorganic materials 0.000 abstract description 4
- 235000010210 aluminium Nutrition 0.000 abstract 2
- 238000005259 measurement Methods 0.000 description 16
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は高速動作の半導体集積回路装置に関し、特に論
理演算の遅延時間性能を簡易に検出し評価するための専
用の発振回路を有している半導体集積回路の回路配置に
関する。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a high-speed operation semiconductor integrated circuit device, and in particular to a semiconductor integrated circuit device having a dedicated oscillation circuit for easily detecting and evaluating the delay time performance of logical operations. Regarding the circuit layout of semiconductor integrated circuits.
従来、この種の半導体集積回路内に配置された遅延時間
測定用発振回路は、1チップごとに遅延時間が測定出来
る様に1チップごとにもうけていた。Conventionally, an oscillation circuit for measuring delay time disposed in this type of semiconductor integrated circuit has been provided for each chip so that the delay time can be measured for each chip.
上述した従来の遅延時間測定用発振回路を有した集積回
路装置ではひとつの集積回路装置にひとつの発振回路を
持っているのでLSIの遅延時間が短かくなった時、発
振回路の発振周波数が高くなり、その発振周波数を測定
可能な低い周波数にするためには発振回路の論理演算素
子の段数を増す必要があり、そのために発振回路が大規
模となり、半導体集積回路の大きな面積をしめるという
欠点がある。In the above-mentioned conventional integrated circuit device having an oscillation circuit for measuring delay time, one integrated circuit device has one oscillation circuit, so when the delay time of the LSI becomes short, the oscillation frequency of the oscillation circuit increases. Therefore, in order to reduce the oscillation frequency to a measurable low frequency, it is necessary to increase the number of logic operation elements in the oscillation circuit, which has the disadvantage that the oscillation circuit becomes large and takes up a large area of the semiconductor integrated circuit. be.
上述した従来の遅延測定用の発振回路を1チップのみで
構成するのに対し、本発明は発振回路を分割して複数の
チップに載せるという独想的内容を有する。While the conventional oscillation circuit for delay measurement described above is constructed of only one chip, the present invention has an original content in that the oscillation circuit is divided and mounted on a plurality of chips.
本発明の半導体集積回路装置は、自励発振回路を内部に
持つ半導体集積回路において、自励発振回路を複数のチ
ップに分割し、各1チップ内に発振の一部のみを有して
いる。A semiconductor integrated circuit device of the present invention is a semiconductor integrated circuit having a self-excited oscillation circuit therein, in which the self-excited oscillation circuit is divided into a plurality of chips, and each chip has only a part of the oscillation.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第1図は本発明の第1の実施例の平面概念図である。第
1図に示すように本実施例はスクライブ線1.電源線2
.接地線3.パッド4.遅延測定用発振回路51本来の
集積回路としての機能をもつ素子領域6.第1のチップ
7、第2のチップ8゜第3のチップ9.信号線10から
構成されている。FIG. 1 is a conceptual plan view of a first embodiment of the present invention. As shown in FIG. 1, this embodiment has a scribe line 1. Power line 2
.. Ground wire 3. Pad 4. Delay measurement oscillation circuit 51 Element region 6 which functions as an original integrated circuit. First chip 7, second chip 8°, third chip 9. It is composed of a signal line 10.
遅延時間測定用発振回路5は、3つのチップ、第1のチ
ップ7、第2のチップ8.第3のチップ9にそれぞれ分
割して載せられた否定論理演算回路を直列につなぐこと
により構成される。例えば各チップには発振回路の一部
としてそれぞれ25段の否定論理回路素子がもうけられ
ており、第1のチップ7にもうけられた前記測定用論理
回路の出力は信号線10を通して第3のチ、ツブ9の測
定用論理回路の入力に電気的に接続されている。又、第
3のチップ9の測定用論理回路の出力は第2のチップ8
の測定用論理回路の入力に接続されて、第2のチップ8
の測定用論理回路の出力は、第1のチップ7の遅延測定
用論理回路の入力に接続されている。このとき互の配線
はアルミでスクライブ線1をまたいでウェハー上に形成
され、アルミ配線により互に電気的に接続されている。The delay time measurement oscillation circuit 5 includes three chips: a first chip 7, a second chip 8. It is constructed by serially connecting negative logic operation circuits separately mounted on the third chip 9. For example, each chip is provided with 25 stages of negative logic circuit elements as part of the oscillation circuit, and the output of the measurement logic circuit provided in the first chip 7 is transmitted through the signal line 10 to the third chip. , electrically connected to the input of the measurement logic circuit of the knob 9. Also, the output of the measurement logic circuit of the third chip 9 is transmitted to the second chip 8.
connected to the input of the measuring logic circuit of the second chip 8
The output of the measuring logic circuit is connected to the input of the delay measuring logic circuit of the first chip 7. At this time, mutual wirings are formed on the wafer using aluminum across the scribe line 1, and are electrically connected to each other by the aluminum wirings.
半導体集積回路装置の良否をウェハー状態で検査する時
、例えば、第1のチップ7のパッド4に針があてられた
時、第2のチップ8.第3のチップ9にも電源線2.接
地線3を通して電力供給が行われ、第2のチップ8.第
3のチップ9の測定用論理回路も動作し、3つのチップ
合せてひとつの発振回路として動作する。この時1段の
論理回路の遅延時間を100ピコ秒であるとすると、測
定される発振周波数は、1チップあたりの論理回路の数
が25段であるから3チップで75段となる。したがっ
て、1/(75X100ピコ秒)−133メガヘルンと
なる。このときひとつの発振回路を分割するチップ数を
任意に選んで1チップあたりの論理演算素子の段数を適
切な数とすることで測定可能な自動発振回路を形成でき
る。When inspecting the quality of a semiconductor integrated circuit device in a wafer state, for example, when a needle is applied to the pad 4 of the first chip 7, the second chip 8. The third chip 9 also has a power line 2. Power is supplied through the ground wire 3 to the second chip 8. The measurement logic circuit of the third chip 9 also operates, and the three chips collectively operate as one oscillation circuit. At this time, assuming that the delay time of one stage of logic circuit is 100 picoseconds, the measured oscillation frequency will be 75 stages for three chips since the number of logic circuits per chip is 25. Therefore, 1/(75×100 picoseconds)−133 megaherns. At this time, a measurable automatic oscillation circuit can be formed by arbitrarily selecting the number of chips into which one oscillation circuit is divided and setting the number of logic operation element stages per chip to an appropriate number.
第2図は本発明の第2の実施例の平面概念図である。第
2図に示すように本実施例はスクライブ線1.遅延測定
用論理回路5.パッド4.第1のチップ7、第2のチッ
プ8.第3のチップ9を含み構成される。この例の場合
、第1のチップ7゜第2のチップ8に分割配置された測
定用論理回路を直列につなぐことによりひとつの発振回
路として動作するように作られている。各チップにはそ
れぞれ25段の遅延測定用の否定論理回路素子が設けら
れている。発振周波数の測定には、各チップの測定用論
理回路の任意のチップ数を直列に電気的に接続し、最終
段の遅延測定用論理回路5の出力を初段の遅延測定用論
理回路の入力に電気的に接続する。そしてそれぞれのチ
ップに電源を供給して、複数のチップ合せてひとつの発
振回路として発振させる。発振周波数の測定は第1の実
施例同様に行えばよい。FIG. 2 is a conceptual plan view of a second embodiment of the present invention. As shown in FIG. 2, this embodiment has scribe lines 1. Logic circuit for delay measurement 5. Pad 4. First chip 7, second chip 8. It is configured to include a third chip 9. In the case of this example, the measurement logic circuits divided and arranged in the first chip 7 degrees and the second chip 8 are connected in series to operate as one oscillation circuit. Each chip is provided with 25 stages of negative logic circuit elements for delay measurement. To measure the oscillation frequency, an arbitrary number of chips of the measurement logic circuit of each chip are electrically connected in series, and the output of the final stage delay measurement logic circuit 5 is connected to the input of the first stage delay measurement logic circuit. Connect electrically. Power is then supplied to each chip, causing the multiple chips to oscillate as one oscillation circuit. The oscillation frequency may be measured in the same manner as in the first embodiment.
以上説明したように本発明は遅延測定用の発振回路を複
数チップに分割して載せることにより、ひとつの集積回
路装置にしめる遅延測定用発振回路の面積を小さくおさ
えることができる。As explained above, in the present invention, by dividing and mounting the oscillation circuit for delay measurement on a plurality of chips, it is possible to reduce the area of the oscillation circuit for delay measurement in one integrated circuit device.
第1図は本発明の第1の実施例の平面概念図、第2図は
第2の実施例の平面概念図である。
1・・・スクライブ線、2・・・電源線、3・・・接地
線、4・・・パッド、5・・・遅延測定用論理回路、6
・・・素子領域、7・・・第1のチップ、8・・・第2
のチップ、9・・・第3のチップ、10・・・信号線、
11・・・第1のチップ、12・・・第2のチップ、1
3・・・第3のチップ。FIG. 1 is a conceptual plan view of a first embodiment of the present invention, and FIG. 2 is a conceptual plan view of a second embodiment. DESCRIPTION OF SYMBOLS 1... Scribe line, 2... Power supply line, 3... Ground line, 4... Pad, 5... Logic circuit for delay measurement, 6
...Element area, 7...First chip, 8...Second chip
chip, 9... third chip, 10... signal line,
11...first chip, 12...second chip, 1
3...Third chip.
Claims (1)
集積回路装置において、前記自励発振回路を複数のチッ
プに分割し、各1チップ内に前記分割した発振回路の一
部のみを設けることを特徴とする半導体集積回路装置。A semiconductor integrated circuit device having a self-excited oscillation circuit and a plurality of chips inside, characterized in that the self-excited oscillation circuit is divided into a plurality of chips, and only a part of the divided oscillation circuit is provided in each chip. Semiconductor integrated circuit device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6960287A JPH063838B2 (en) | 1987-03-23 | 1987-03-23 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6960287A JPH063838B2 (en) | 1987-03-23 | 1987-03-23 | Semiconductor integrated circuit device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS63234553A true JPS63234553A (en) | 1988-09-29 |
JPH063838B2 JPH063838B2 (en) | 1994-01-12 |
Family
ID=13407548
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6960287A Expired - Lifetime JPH063838B2 (en) | 1987-03-23 | 1987-03-23 | Semiconductor integrated circuit device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH063838B2 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1991019318A1 (en) * | 1990-06-05 | 1991-12-12 | Seiko Epson Corporation | Semiconductor device provided with logical circuit for measuring delay |
WO2001099194A2 (en) * | 2000-06-16 | 2001-12-27 | Infineon Technologies North America Corp. | Semiconductor arrangement |
WO2001099188A3 (en) * | 2000-06-16 | 2003-04-24 | Infineon Technologies Corp | Semiconductor package and method |
-
1987
- 1987-03-23 JP JP6960287A patent/JPH063838B2/en not_active Expired - Lifetime
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1991019318A1 (en) * | 1990-06-05 | 1991-12-12 | Seiko Epson Corporation | Semiconductor device provided with logical circuit for measuring delay |
WO2001099194A2 (en) * | 2000-06-16 | 2001-12-27 | Infineon Technologies North America Corp. | Semiconductor arrangement |
WO2001099194A3 (en) * | 2000-06-16 | 2002-05-02 | Infineon Technologies Corp | Semiconductor arrangement |
WO2001099188A3 (en) * | 2000-06-16 | 2003-04-24 | Infineon Technologies Corp | Semiconductor package and method |
US6730989B1 (en) | 2000-06-16 | 2004-05-04 | Infineon Technologies Ag | Semiconductor package and method |
US6815803B1 (en) | 2000-06-16 | 2004-11-09 | Infineon Technologies Ag | Multiple chip semiconductor arrangement having electrical components in separating regions |
US7060529B2 (en) | 2000-06-16 | 2006-06-13 | Infineon Technologies Ag | Multiple chip semiconductor arrangement having electrical components in separating regions |
Also Published As
Publication number | Publication date |
---|---|
JPH063838B2 (en) | 1994-01-12 |
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