JPS63234553A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To prevent the occupying of large areas in a semiconductor integrated circuit of oscillation circuits by dividing a self-oscillation circuit into a plurality of chips and forming only one part of the oscillation circuits divided into each one chip. CONSTITUTION:In a semiconductor integrated circuit, the inside of which has a self-oscillation circuit, the self-oscillation circuit is divided into a plurality of chips, and only one part of oscillation is shaped into each one chip. That is, an oscillation circuit 5 for measuring the delay time is constituted by connecting NOT logic operation circuits, which are respectively partitioned into a first chip 7, a second chip 8 and a third chip 9 of three chips and placed, and mutual wirings are shaped onto a wafer, crossing scribing lines 1 by alumi num, and mutually connected electrically by aluminum wirings. The number of chips dividing one oscillation circuit is selected arbitrarily at that time, and the number of the stages of logical operators per one chip is brought to a proper number, thus forming a measurable self-oscillation circuit. Accordingly, the area of the oscillation circuit 5 for measuring delay occupying in one inte grated circuit device can be inhibited to a small value.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a high-speed operation semiconductor integrated circuit device, and in particular to a semiconductor integrated circuit device having a dedicated oscillation circuit for easily detecting and evaluating the delay time performance of logical operations. Regarding the circuit layout of semiconductor integrated circuits.

[Conventional technology]

Conventionally, an oscillation circuit for measuring delay time disposed in this type of semiconductor integrated circuit has been provided for each chip so that the delay time can be measured for each chip.

[Problem that the invention seeks to solve]

In the above-mentioned conventional integrated circuit device having an oscillation circuit for measuring delay time, one integrated circuit device has one oscillation circuit, so when the delay time of the LSI becomes short, the oscillation frequency of the oscillation circuit increases. Therefore, in order to reduce the oscillation frequency to a measurable low frequency, it is necessary to increase the number of logic operation elements in the oscillation circuit, which has the disadvantage that the oscillation circuit becomes large and takes up a large area of the semiconductor integrated circuit. be.

While the conventional oscillation circuit for delay measurement described above is constructed of only one chip, the present invention has an original content in that the oscillation circuit is divided and mounted on a plurality of chips.

[Means for solving problems]

A semiconductor integrated circuit device of the present invention is a semiconductor integrated circuit having a self-excited oscillation circuit therein, in which the self-excited oscillation circuit is divided into a plurality of chips, and each chip has only a part of the oscillation.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a conceptual plan view of a first embodiment of the present invention. As shown in FIG. 1, this embodiment has a scribe line 1. Power line 2
．． Ground wire 3. Pad 4. Delay measurement oscillation circuit 51 Element region 6 which functions as an original integrated circuit. First chip 7, second chip 8°, third chip 9. It is composed of a signal line 10.

The delay time measurement oscillation circuit 5 includes three chips: a first chip 7, a second chip 8. It is constructed by serially connecting negative logic operation circuits separately mounted on the third chip 9. For example, each chip is provided with 25 stages of negative logic circuit elements as part of the oscillation circuit, and the output of the measurement logic circuit provided in the first chip 7 is transmitted through the signal line 10 to the third chip. , electrically connected to the input of the measurement logic circuit of the knob 9. Also, the output of the measurement logic circuit of the third chip 9 is transmitted to the second chip 8.
connected to the input of the measuring logic circuit of the second chip 8
The output of the measuring logic circuit is connected to the input of the delay measuring logic circuit of the first chip 7. At this time, mutual wirings are formed on the wafer using aluminum across the scribe line 1, and are electrically connected to each other by the aluminum wirings.

When inspecting the quality of a semiconductor integrated circuit device in a wafer state, for example, when a needle is applied to the pad 4 of the first chip 7, the second chip 8. The third chip 9 also has a power line 2. Power is supplied through the ground wire 3 to the second chip 8. The measurement logic circuit of the third chip 9 also operates, and the three chips collectively operate as one oscillation circuit. At this time, assuming that the delay time of one stage of logic circuit is 100 picoseconds, the measured oscillation frequency will be 75 stages for three chips since the number of logic circuits per chip is 25. Therefore, 1/(75×100 picoseconds)−133 megaherns. At this time, a measurable automatic oscillation circuit can be formed by arbitrarily selecting the number of chips into which one oscillation circuit is divided and setting the number of logic operation element stages per chip to an appropriate number.

FIG. 2 is a conceptual plan view of a second embodiment of the present invention. As shown in FIG. 2, this embodiment has scribe lines 1. Logic circuit for delay measurement 5. Pad 4. First chip 7, second chip 8. It is configured to include a third chip 9. In the case of this example, the measurement logic circuits divided and arranged in the first chip 7 degrees and the second chip 8 are connected in series to operate as one oscillation circuit. Each chip is provided with 25 stages of negative logic circuit elements for delay measurement. To measure the oscillation frequency, an arbitrary number of chips of the measurement logic circuit of each chip are electrically connected in series, and the output of the final stage delay measurement logic circuit 5 is connected to the input of the first stage delay measurement logic circuit. Connect electrically. Power is then supplied to each chip, causing the multiple chips to oscillate as one oscillation circuit. The oscillation frequency may be measured in the same manner as in the first embodiment.

〔Effect of the invention〕

As explained above, in the present invention, by dividing and mounting the oscillation circuit for delay measurement on a plurality of chips, it is possible to reduce the area of the oscillation circuit for delay measurement in one integrated circuit device.

[Brief explanation of drawings]

FIG. 1 is a conceptual plan view of a first embodiment of the present invention, and FIG. 2 is a conceptual plan view of a second embodiment. DESCRIPTION OF SYMBOLS 1... Scribe line, 2... Power supply line, 3... Ground line, 4... Pad, 5... Logic circuit for delay measurement, 6
...Element area, 7...First chip, 8...Second chip
chip, 9... third chip, 10... signal line,
11...first chip, 12...second chip, 1
3...Third chip.

Claims (1)

[Claims] A semiconductor integrated circuit device having a self-excited oscillation circuit and a plurality of chips inside, characterized in that the self-excited oscillation circuit is divided into a plurality of chips, and only a part of the divided oscillation circuit is provided in each chip. Semiconductor integrated circuit device.