JPS61187354A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPS61187354A
JPS61187354A JP60027841A JP2784185A JPS61187354A JP S61187354 A JPS61187354 A JP S61187354A JP 60027841 A JP60027841 A JP 60027841A JP 2784185 A JP2784185 A JP 2784185A JP S61187354 A JPS61187354 A JP S61187354A
Authority
JP
Japan
Prior art keywords
pad
bonding pad
wiring pattern
scribe line
chips
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60027841A
Other languages
Japanese (ja)
Inventor
Masahiro Ouchi
大内　雅弘
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP60027841A priority Critical patent/JPS61187354A/en
Publication of JPS61187354A publication Critical patent/JPS61187354A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Abstract

PURPOSE:To facilitate the inspection of devices in their wafer stage by a method wherein each of the IC chips formed on a semiconductor substrate is provided with a wiring pattern and the wiring pattern and a bonding pad located on the wiring pattern are connected to a dummy pad provided on a scribe line located between the IC chips. CONSTITUTION:Each of the multiplicity of IC chips 5 is provided with a bonding pad 1 and wiring patterns 2 made of Al, Au, or the like are connected to both sides of the bonding pad 1. Next, within a dividing scribe line 3 provided between the IC chips 5, a dummy pad 4 is installed made of the same material as the pad 1, and a wiring pattern 2 linked to the pad 1 is connected to the dummy pad 4. The pad 1 is designed to be dimensionally small to reduce parasitic capacity. The pad 4, however, is made larger so that the probe of a probe card may land on the pad 4 with ease for inspection. Finally, the pattern 2 is disconnected simultaneously with a scribe work.

Description

【発明の詳細な説明】 ＋１）　　発明の属する技術分野の説明本発明は、高周
波用の半導体集積回路に関し、特にウェハー状態で検査
可能なボンディングパッドに関する。DETAILED DESCRIPTION OF THE INVENTION +1) Description of the technical field to which the invention pertains The present invention relates to a high frequency semiconductor integrated circuit, and particularly to a bonding pad that can be tested in a wafer state.

（２）　　従来技術の説明 従来、高周波用の半導体集積回路装置（以下ＭＭＩＣと
称す）のボンディングパッドは第５図に示す様に、ＩＣ
のサブストレート８とボンディングパッド１の間に絶縁
層９を介して生じる寄生容１ｉ７ｔ−減少する目的で、
可能なかぎりその面積を小さくしていた。(2) Description of the prior art Conventionally, the bonding pad of a high frequency semiconductor integrated circuit device (hereinafter referred to as MMIC) is
For the purpose of reducing the parasitic capacitance 1i7t produced between the substrate 8 and the bonding pad 1 through the insulating layer 9,
The area was kept as small as possible.

また、一般にＩＣの製造過程において、ウェハーの状態
でＩＣチップが正常に機能をはたしているかチェックす
る目的でＩＣテスター等により、検査を行なう場合が多
い。この場合、検査の方法は、第６図に示すＩＣのボン
ディングパッド１２の位置と同一位置に配置された複数
本の探針１１を有するプローブカード１０を、第７図に
示す様に、ＩＣのボンディングパッドに接触させて信号
又はバイアス電源を探針１３よシエＣテスターからＩＣ
に供給し、ＩＣの機能を検査するものである。この方法
の欠点は、プローブカード上のすべての探針がＩＣ上の
ボンディングパッドと物理的に同一位置になければなら
ない。この関係はプローブカードを製造する際に裸針金
固定する機械的精度で決まってしまう。したがって、ウ
ェハー状態で検査を行なう場合、探針どうしが接触せず
にかつ量産レベルに見合う程度の精度でプローブカード
全製造とすると、ボンディングパッドの面積がある程度
広（なり、かつ、パッドとパッドの間隔も大きくなる。Further, in general, in the process of manufacturing an IC, an IC tester or the like is often used to perform an inspection in order to check whether the IC chip is functioning normally in the wafer state. In this case, the inspection method is to insert a probe card 10 having a plurality of probes 11 arranged at the same position as the bonding pad 12 of the IC shown in FIG. Contact the bonding pad and apply a signal or bias power source to the probe 13 from the C tester to the IC.
This is used to test the functionality of the IC. The disadvantage of this method is that all probes on the probe card must be physically co-located with bonding pads on the IC. This relationship is determined by the mechanical precision with which the bare wire is fixed when manufacturing the probe card. Therefore, when testing in the wafer state, if all probe cards are manufactured without the probes touching each other and with an accuracy commensurate with mass production, the area of the bonding pads will be wide to some extent (and the area between the pads will be The spacing also increases.

パッド間隔が大きくなる事は、ＭＭＩＣではさほど問題
にならないが、パッド面積が広くなることは、′４Ｐ生
容量が大きくなることであるから、ＭＭＩＣとしては大
きな問題となる。従来のＭＭＩＣでは、パッド面積が狭
い為にプローブカードが使えず、ウェハー状態での検査
が行なえなかったこの為に、組み立て後の歩留りが悪（
なるという欠点があった。Increasing the pad spacing is not so much of a problem in MMICs, but increasing the pad area increases the '4P raw capacitance, which is a big problem in MMICs. With conventional MMICs, probe cards cannot be used due to the small pad area, and testing in the wafer state cannot be performed.As a result, the yield after assembly is poor (
There was a drawback.

（３）発明の詳細な説明 本発明は、本来の機能含有するボンディングパッドとス
クライブ線上又はスクライブ線ヲ介して接続された疑似
のボンディングパッドを設けることによシ、ウェハー状
態での検査を可能にし、組み立て歩留シが良い半導体集
積回路を提供するものである。(3) Detailed Description of the Invention The present invention enables inspection in the wafer state by providing a bonding pad having an original function and a pseudo bonding pad connected on or through a scribe line. The present invention provides a semiconductor integrated circuit with a high assembly yield.

（４）発明の構成 本発明は、第１のボンディングパッドとスクライブ線上
に′ｙ４１のボンディングパッドと同一工程で製造され
た第２のパッドを設け、第１＃第２のパッドが配線用の
パターンによシ接続されているか、又は、第１のボンデ
ィングパッドとスクライブ線上に存在する配線パターン
を介して第１のボンディングバードと同一工程で製造さ
れた第２のパッドを有することｔ−＊ｇとする。(4) Structure of the Invention The present invention provides a second pad manufactured in the same process as the bonding pad 'y41 on the first bonding pad and the scribe line, and the first #second pad is a wiring pattern. or has a second pad manufactured in the same process as the first bonding pad through a wiring pattern existing on the first bonding pad and the scribe line. do.

（５）　　この発明の詳細な説明 次に本発明の実施例について、図面を参照して説明する
。(5) Detailed Description of the Invention Next, embodiments of the invention will be described with reference to the drawings.

第１図を参照すると１本発明の第１の実施例は、ボンデ
ィングパッド１と、アルミ又は金等によシ製造された配
線パターン２とＩＣを切り離す際の分離領域にあたるス
クライブ＠３と配線パターン２によシパッド１と接続さ
れかつ、パッド１と同じ１根で製造されたアルミ又は金
の領域４（疑似パッドと称する）と、本来のＩＣ領域５
（切断後チップとなるところ）とを含む。本実施例では
、１なるボンディングパッドはを生容量を減少させる目
的で３０μ７ＦＬＸ３０μｍにしている。したがって、
このパッドではプローブカードによるウェハー検査は離
かしいしかし、スクライブ線中に１よシも面積が大きく
かつ、ボンディングパッドと同じ工程で（例えば、アル
ミ、金等）疑似のパッドを設けることにより、ウェハー
状態では、プローブカードの探針を４の位置にすれば、
直流的な検査は可能になる。Referring to FIG. 1, the first embodiment of the present invention consists of a bonding pad 1, a wiring pattern 2 made of aluminum or gold, a scribe@3 which is a separation area when separating an IC, and a wiring pattern. 2, an aluminum or gold region 4 (referred to as a pseudo pad) connected to the pad 1 and manufactured from the same base as the pad 1, and an original IC region 5.
(the part that becomes the chip after cutting). In this embodiment, the bonding pad 1 is 30μ7FL x 30μm in order to reduce the raw capacitance. therefore,
This pad makes it difficult to inspect the wafer with a probe card.However, by providing a pseudo pad (for example, aluminum, gold, etc.) in the same process as the bonding pad, which has a larger area than the one in the scribe line, it is possible to inspect the wafer with a probe card. Now, if you set the probe card's probe to position 4,
Direct current inspection becomes possible.

ウェハー状態での検査が終了すれば、領域３を切断し、
ＩＣチップを分離する。この時、スクライブ線３上にあ
るパターン２は切断されパッドｌと疑似パッド４とは切
断される。この為に、ＩＣチップとなった時は、第２図
に示した様に、寄生容量としては、部分６が付加される
のみである。パッド】と疑似パッド４ｔ−あらかじめ接
続して２（パターン２は、可能なかぎり細くしておけば
、寄生容量の増加は無視できる。When the inspection in the wafer state is completed, area 3 is cut,
Separate the IC chip. At this time, the pattern 2 on the scribe line 3 is cut, and the pad 1 and the pseudo pad 4 are cut. For this reason, when it becomes an IC chip, only the portion 6 is added as a parasitic capacitance, as shown in FIG. If the pattern 2 (pattern 2) is made as thin as possible, the increase in parasitic capacitance can be ignored.

次にｗＩ３図を参照して第２の実施例について説明する
。Next, a second embodiment will be described with reference to FIG. wI3.

第２の実施例は、スクライプ＠３が狭い為にスクライブ
−中に疑似パッドが置けない場合であり、ＩＣ本来の領
域５に疑似パッド４を置きスクライブ線中を通る配線パ
ターン２で接続したものである。The second embodiment is a case in which a pseudo pad cannot be placed inside the scribe because the scribe@3 is narrow, and a pseudo pad 4 is placed in the original area 5 of the IC and connected by a wiring pattern 2 passing through the scribe line. It is.

ウェハー状態での検査は、前記実施例と同様に４なる疑
似パッドにプローブカードの探針を当てて検査を行なう
。４＊査が終了して、スクライブ線にそってＩＣチップ
を分離すると、第４図に示す様にな９．寄生容量として
は、前記実施例１と同様に、　る部分６のみであり、配
線６の幅を可能なかぎり狭くしておけば％寄生容量は無
視できることになる。Inspection in the wafer state is carried out by applying the probe of the probe card to the pseudo pad numbered 4, as in the previous embodiment. 4* When the inspection is completed and the IC chip is separated along the scribe line, it becomes 9. as shown in Fig. 4. As in the first embodiment, the parasitic capacitance is only in the portion 6, and if the width of the wiring 6 is made as narrow as possible, the parasitic capacitance can be ignored.

（６）　　発明の詳細な説明 本発明は、以上説明したように、疑似パッドをスクライ
ブ線上又はＩＣチップ上に置き、かつスクライブ線上を
通る配線パターンで本来のボンディングパッドと接続す
ることによシ、ボンディングパッドが小さい高周波用Ｉ
Ｃの性能を害うことなくウェハー状態での検査が可能に
なシ、組み立て後の歩留りが向上する効果がある。(6) Detailed Description of the Invention As explained above, the present invention provides a bonding pad by placing a pseudo pad on a scribe line or an IC chip and connecting it to an original bonding pad with a wiring pattern passing over the scribe line. High frequency I with small bonding pad
This makes it possible to inspect the wafer without impairing the performance of C, and has the effect of improving the yield after assembly.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の第１の実施例を示す平面図、第２図は
第１図に示したウェハーをスクライブ線に沿って切断し
た時の状態を示す平面図、第３図は本発明のａ［２の実
施例を示す平面図、第４図は第３図に示したウェハーを
スクライブ線に沿って切断した時の状態を示す平面図、
第５図はボンディングパッドとＩＣのサブストレート間
の寄生容量を示した例を示す断面図、第６図はプローブ
カードとＩＣチップ上のボンディングパッドの関係を示
した平面図、第７図はプローブカードの探針とボンディ
ングパッドの関係金示した側面図である。 尚、図において、１・・・・・・ボンディングパッド。 ２・・・・・・配線パターン、３・・・・・・スクライ
ブ線％　４・・・・・・疑似パッド、５・・・・−Ｉ　
Ｃチップ、６・・・・・・スクライブにより残った配線
パターン、７・・・・・・ボンディングパッドとサブス
トレート間の寄生容量、８・・・・・・サブストレート
、９・・・・・・絶縁層、ｌＯ・・・・・・プローブカ
ード、１１・・・・・・プローブカードの探針。 １２・・・・・・ボンディングパッド％　］３・・・・
・・プローブカードの探針。 第１図 第２図 第３図 第４図 第５図 第６図 第７図FIG. 1 is a plan view showing a first embodiment of the present invention, FIG. 2 is a plan view showing the state when the wafer shown in FIG. 1 is cut along the scribe line, and FIG. 3 is a plan view showing the present invention. Fig. 4 is a plan view showing the state when the wafer shown in Fig. 3 is cut along the scribe line;
Figure 5 is a cross-sectional view showing an example of parasitic capacitance between the bonding pad and the IC substrate, Figure 6 is a plan view showing the relationship between the probe card and the bonding pad on the IC chip, and Figure 7 is the probe. FIG. 3 is a side view showing the relationship between the probe and the bonding pad of the card. In the figure, 1... bonding pad. 2...Wiring pattern, 3...Scribe line% 4...Pseudo pad, 5...-I
C chip, 6... Wiring pattern left after scribing, 7... Parasitic capacitance between bonding pad and substrate, 8... Substrate, 9... - Insulating layer, lO...probe card, 11... probe of probe card. 12...Bonding pad% ]3...
... Probe card probe. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7

Claims (2)

【特許請求の範囲】[Claims] （１）半導体基板のペレットとなる部分に設けられた第
１のボンディングパッドと、該基板のスクライズ線上に
設けられた前記第１のボンディングパッドと同一の材質
の第２のボンディングパッドと、該第１および第２のボ
ンディングパッドを接続した配線用のパターンとを有す
ることを特徴とする半導体集積回路装置。(1) A first bonding pad provided on a portion of the semiconductor substrate that will become a pellet; a second bonding pad made of the same material as the first bonding pad provided on the scribe line of the substrate; 1. A semiconductor integrated circuit device comprising a wiring pattern connecting first and second bonding pads. （２）第１のボンディングパッドとスクライブ線上に存
在する配線用パターンを介して第１のボンディングパッ
ドと同一の材質の第２のパッドとを有することを特徴と
する半導体集積回路装置。(2) A semiconductor integrated circuit device characterized by having a second pad made of the same material as the first bonding pad via a wiring pattern existing on a scribe line between the first bonding pad and the first bonding pad.
JP60027841A 1985-02-15 1985-02-15 Semiconductor integrated circuit device Pending JPS61187354A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60027841A JPS61187354A (en) 1985-02-15 1985-02-15 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60027841A JPS61187354A (en) 1985-02-15 1985-02-15 Semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPS61187354A true JPS61187354A (en) 1986-08-21

Family

ID=12232140

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60027841A Pending JPS61187354A (en) 1985-02-15 1985-02-15 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPS61187354A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6373536A (en) * 1986-09-16 1988-04-04 Seiko Epson Corp Semiconductor integrated circuit
US5285082A (en) * 1989-11-08 1994-02-08 U.S. Philips Corporation Integrated test circuits having pads provided along scribe lines
DE19835840B4 (en) * 1997-12-29 2006-03-16 LG Semicon Co., Ltd., Cheongju Manufacturing method for a semiconductor chip
JP2007234933A (en) * 2006-03-02 2007-09-13 Ricoh Co Ltd Semiconductor wafer, semiconductor device, and method for manufacturing semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6373536A (en) * 1986-09-16 1988-04-04 Seiko Epson Corp Semiconductor integrated circuit
US5285082A (en) * 1989-11-08 1994-02-08 U.S. Philips Corporation Integrated test circuits having pads provided along scribe lines
DE19835840B4 (en) * 1997-12-29 2006-03-16 LG Semicon Co., Ltd., Cheongju Manufacturing method for a semiconductor chip
JP2007234933A (en) * 2006-03-02 2007-09-13 Ricoh Co Ltd Semiconductor wafer, semiconductor device, and method for manufacturing semiconductor device

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