JPS6373536A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

Info

Publication number
JPS6373536A
JPS6373536A JP61217756A JP21775686A JPS6373536A JP S6373536 A JPS6373536 A JP S6373536A JP 61217756 A JP61217756 A JP 61217756A JP 21775686 A JP21775686 A JP 21775686A JP S6373536 A JPS6373536 A JP S6373536A
Authority
JP
Japan
Prior art keywords
cutting
terminal
input
slit
output terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61217756A
Other languages
Japanese (ja)
Inventor
Kunio Katsuno
勝野　邦夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP61217756A priority Critical patent/JPS6373536A/en
Publication of JPS6373536A publication Critical patent/JPS6373536A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4899—Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85007—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a permanent auxiliary member being left in the finished device, e.g. aids for holding or protecting the wire connector during or after the bonding process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Abstract

PURPOSE:To exclude failures like the cutting remnant at the time of cutting process without deteriorating the functions of input-output terminals arranged in a scribe region, by a method wherein a terminal (input-output terminal) which is formed in a scribe region and intended for delivering and receiving of signal for external part is provided with slits whose one segment is shorter than or equal to a specified length. CONSTITUTION:An input-output terminal arranged in a scribe region 2 is provided with slits which are vertical to the direction of cutting. As the result of arrangement of slits in the input-output terminal 1, it does not occur that a continuous force is applied, at the time of cutting, to a metal material constituting the terminal. As the result, both cutting remnant and exfoliation are reduced. When the slit width is made wider, the cutting force applying to one terminal becomes smaller and the cutting remant is reduced. However, when it is necessary to make a pin and the like bring into contact with the terminal, the case where the contact is impossible happens, if the slit is made wider than a necessary width, and the terminal cannot satisfy its functions. Consequently, 20mum or less is suitable for the width of slit.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体集積回路の入出力端子の形状に関する
。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the shape of input/output terminals of semiconductor integrated circuits.

〔発明の概−〕[Summary of the invention]

半導体基板上に形成された複数の集積回路チップを切ル
離すための切断領域（スクライブ領域）上に形成された
外部との信号の受授を目的とした端子Ｃ以下入出力端子
という）を１片の長さが２０μｍ以下のスリットを持っ
た形状で構成する〔従来の技術〕 第５図に従来のスクライブ領域上の入出力端子の形状の
一例を示す。スクライブ上の入出力端子も、スクライブ
領域以外の入出力端子と同様に、入出力端子部分は全体
がすきまのない形状となっていた。Terminal C (hereinafter referred to as input/output terminal) formed on the cutting area (scribe area) for separating multiple integrated circuit chips formed on a semiconductor substrate and intended for receiving signals from the outside is 1. [Prior art] Figure 5 shows an example of the shape of a conventional input/output terminal on a scribe area. Like the input/output terminals on the scribe area, the entire input/output terminal part had a shape with no gaps.

〔発明が解決しようとする問題点及び目的〕スクライブ
領域は、集積回路チップをひとつひとつに分離するため
の切断（ダイシング）領域であるため、そこに形成され
たパターンも同時に切断される。スクライブ領域に、信
号の入出力端子を形成した場合、入出力環子は、主に金
属材料で形成されるため、金属材料特有の性質、すなわ
ち、ねばりのため切断残りあるいは、剥離が生ずる、第
６図に切断残りの例を断面図で示す。また、第７′図に
剥離状態の例を示す。切断残りで特に問題となるのは、
第８図に示したように、リードフレームへのチップの固
定の際、切断残りのある金属部分に応力が集中し、チッ
プがかけてしまうことである。ここで１は端子、４は押
え装置、５はリードフレームを示す、また、剥離による
問題は、第９図に示した如く、リードフレームあるーは
信号引き出し線とのシ冒−トである。ここで１は端子、
６は引き出し線を示す。本発明は、かかる問題点を解決
し、半導体集積回路の歩留向上を目的とする。[Problems and Objectives to be Solved by the Invention] Since the scribe area is a dicing area for separating integrated circuit chips one by one, the patterns formed there are also cut at the same time. When signal input/output terminals are formed in the scribe area, the input/output ring is mainly made of metal material, so it is difficult to avoid cutting residue or peeling due to the properties peculiar to metal materials. FIG. 6 shows a cross-sectional view of an example of the remaining portion after cutting. Further, an example of a peeled state is shown in FIG. 7'. A particular problem with uncut parts is
As shown in FIG. 8, when the chip is fixed to the lead frame, stress is concentrated on the metal portion that remains uncut, and the stress is applied to the chip. Here, 1 is a terminal, 4 is a holding device, and 5 is a lead frame.The problem caused by peeling is the impact on the lead frame or the signal lead-out line, as shown in FIG. Here 1 is a terminal,
6 indicates a lead line. The present invention aims to solve these problems and improve the yield of semiconductor integrated circuits.

〔問題を解決するための手段〕[Means to solve the problem]

スクライブ領域に形成する入出力端子をスリットの入っ
た形状で構成することにより、信号の受授には全く影響
なく、かつ、切断面積を小さくす、ることにより、切断
残りあるいは、剥離を少なくする方法である。By configuring the input/output terminals formed in the scribe area with a slit shape, there is no effect on signal reception at all, and the cutting area is reduced, reducing uncut residue or peeling. It's a method.

〔実施例〕〔Example〕

以下実施例に基づいて、詳細に説明する。第１図から第
３図に、本発明のスクライブ領域に設置する入出力端子
の形状例を示す、第１図及び第２２図は、切断方向に垂
直にスリットを入れた形状である。＃１３図は、垂直方
向及び水平方向にスリットを入れた形状である。第４図
は、＠１図の形状の端子を切断した場合の断面図である
。１は、端子、２はスクライブ領域、３は切断する領域
である０本発明によるスリットを入出力端子に入れるこ
とにより、切断時、端子を構成して■る金属材料に、連
続して力が加わることが無くなる。その結果、切断残り
は少なくなり、また、剥離することも少なくなる。The following will be described in detail based on examples. 1 to 3 show examples of shapes of input/output terminals installed in the scribe area of the present invention. FIGS. 1 and 22 show shapes in which slits are made perpendicular to the cutting direction. Figure #13 shows a shape with slits in the vertical and horizontal directions. FIG. 4 is a cross-sectional view of the terminal having the shape shown in FIG. 1 is the terminal, 2 is the scribe area, and 3 is the area to be cut. By inserting the slit according to the present invention into the input/output terminal, force is continuously applied to the metal material that constitutes the terminal during cutting. There will be no more to join. As a result, there will be less cutting residue and less peeling.

スリットの幅を、広くすれば、ひとつの端子に加わる切
断力が少なくなり、切断残り等は少なくなるが、必要以
上に広くすると、針等で端子に接触する必要がある場合
に、接触できな一場合も生じ、入出力端子としての役割
を果さなくなるためスリットの幅は、２０μ溝以下が適
当である。If the width of the slit is widened, the cutting force applied to one terminal will be reduced, and there will be less uncut material, but if the slit is made wider than necessary, it may be difficult to contact the terminal with a needle, etc. If this happens, the slit will no longer function as an input/output terminal, so the appropriate width of the slit is 20 μm or less.

〔発明の効果〕〔Effect of the invention〕

本発明は、スクライブ領域に設けられた入出力端子の機
能を損うことなく、切断時に切断残り等゛　の不具合を
無くすことが可能であるため、半導体集積回路の歩留向
上の効果が得られる。The present invention can eliminate defects such as uncut portions during cutting without impairing the functions of input/output terminals provided in the scribe area, and therefore can improve the yield of semiconductor integrated circuits. .

【図面の簡単な説明】[Brief explanation of the drawing]

ｉ３Ｎ４図、第２図、第３図は、本発明の入出力端子で
ある。第４図は、第１図の入出力端子を切断した後の断
面図である。第５図は、従来の入出力端子である。第６
図は、第５図の入出力端子を切断した後の切断残りの例
である。第７図は、第５図の入出力端子を切断した後の
剥離の状態を示す、第ａ図Ｇ；ｔ、リードフレームへの
チップの固定方法の一例を示したものである。第９図は
、剥離した金属片と引き出し線とのシ１−トの一例を示
したものである。 １・・・・・・入出力端子 ２・・・・・・スクライブ領域 以上 出願人　セイコーエプソン株式会社 代理人　弁理士最上務（他１名） 第１図 第２図 に３図 第　４（２） 第　５図 第６０　　　　［区i3N4, FIG. 2, and FIG. 3 are input/output terminals of the present invention. FIG. 4 is a cross-sectional view of the input/output terminal shown in FIG. 1 after being cut away. FIG. 5 shows a conventional input/output terminal. 6th
The figure shows an example of what remains after cutting the input/output terminals shown in FIG. 5. FIG. 7 shows an example of a method of fixing a chip to a lead frame; FIG. FIG. 9 shows an example of a sheet of peeled metal pieces and lead wires. 1...Input/output terminal 2...Scribe area or above Applicant Seiko Epson Co., Ltd. agent Representative Patent Attorney Mogami (1 other person) Figure 1, Figure 2, Figure 3, Figure 4 (2) ) Figure 5 60 [District

Claims (1)

【特許請求の範囲】[Claims] 半導体集積回路チップとして切り離すための、スクライ
ブ領域を有し、かつ該スクライブ領域上に、信号の入力
あるいは出力端子を有する半導体集積回路において、該
入力あるいは出力端子の形状が、１片の長さが２０μｍ
以下のスリットを有する形状であることを特徴とする半
導体集積回路。In a semiconductor integrated circuit that has a scribe area and has a signal input or output terminal on the scribe area to be separated into a semiconductor integrated circuit chip, the shape of the input or output terminal is such that the length of one piece is 20μm
A semiconductor integrated circuit characterized by having a shape having the following slits.
JP61217756A 1986-09-16 1986-09-16 Semiconductor integrated circuit Pending JPS6373536A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61217756A JPS6373536A (en) 1986-09-16 1986-09-16 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61217756A JPS6373536A (en) 1986-09-16 1986-09-16 Semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPS6373536A true JPS6373536A (en) 1988-04-04

Family

ID=16709251

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61217756A Pending JPS6373536A (en) 1986-09-16 1986-09-16 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS6373536A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03139862A (en) * 1989-10-25 1991-06-14 Fujitsu Ltd Semiconductor device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5643741A (en) * 1979-09-17 1981-04-22 Nec Corp Semiconductor wafer
JPS5643740A (en) * 1979-09-17 1981-04-22 Nec Corp Semiconductor wafer
JPS61187354A (en) * 1985-02-15 1986-08-21 Nec Corp Semiconductor integrated circuit device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5643741A (en) * 1979-09-17 1981-04-22 Nec Corp Semiconductor wafer
JPS5643740A (en) * 1979-09-17 1981-04-22 Nec Corp Semiconductor wafer
JPS61187354A (en) * 1985-02-15 1986-08-21 Nec Corp Semiconductor integrated circuit device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03139862A (en) * 1989-10-25 1991-06-14 Fujitsu Ltd Semiconductor device

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