JPH01186652A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH01186652A
JPH01186652A JP63005918A JP591888A JPH01186652A JP H01186652 A JPH01186652 A JP H01186652A JP 63005918 A JP63005918 A JP 63005918A JP 591888 A JP591888 A JP 591888A JP H01186652 A JPH01186652 A JP H01186652A
Authority
JP
Japan
Prior art keywords
wiring
pad electrode
pad
dicing
bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP63005918A
Other languages
Japanese (ja)
Other versions
JP2867138B2 (en
Inventor
Hajime Nara
奈良　肇
Tsugumi Konno
今野　次視
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP591888A priority Critical patent/JP2867138B2/en
Publication of JPH01186652A publication Critical patent/JPH01186652A/en
Application granted granted Critical
Publication of JP2867138B2 publication Critical patent/JP2867138B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]

Abstract

PURPOSE:To prevent peeling of a metal or metal alloy as well as contact of burr with wiring materials from occurring by performing patterning to the inside simultaneously with wiring at the scribe part and etching of PAD electrode itself. CONSTITUTION:A semiconductor element for monitoring is formed at the same time when the semiconductor element is formed and an Al wiring and PAD electrode 1 which are formed for confirming characteristics of semiconductor elements for monitoring are formed simultaneously in a form including a pattern which enables a part 2 without a parallel Al in dicing direction. Then, after the characteristics are confirmed using the PAD electrode 1, it flows into dicing process, the dicing process ends, and packaging process is completed without a burr 5 of scribe PAD being in contact with a bonding wire 4 when an external electrode and a bonding PAD 3 within chip are connected by a bonding wire 4. It prevents contact between bonding wire and burr in packaging process from occurring for reducing bonding failure.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置に関し、特に半導体基板のスクライ
ブ部分における配線、及びＰＡＤ電極構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to wiring in a scribe portion of a semiconductor substrate and a PAD electrode structure.

〔従来の技術〕[Conventional technology]

従来のスクライブ部分の配線及びＰＡＤｔ＆は、その内
部がパターニングされていない、−面に金属あるいは、
金属合金で構成された構造のものであった。The wiring and PADt& of the conventional scribe part are not patterned inside, and the - side is made of metal or
It was constructed of a metal alloy.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかし、前述の従来技術では、ダイシングを実施する事
により、金属あるいは金属合金がめくれ上がり、実装工
程におけるボンディングワイヤー等の配線材料と接触す
る事で不良となる問題点があった。However, in the above-mentioned conventional technology, there is a problem in that the metal or metal alloy is rolled up by dicing and comes into contact with wiring materials such as bonding wires in the mounting process, resulting in defects.

本発明はこの様な問題点を解決するもので、その目的と
する所は、金属あるいは金属合金のめくれ上がりである
パリを低減するようなスクライブ上の配線及びＰＡＤｔ
極構造全構造する事にある。The present invention is intended to solve these problems, and its purpose is to improve wiring and PADt on scribes to reduce the occurrence of curling up of metal or metal alloys.
It consists in having a polar structure and a whole structure.

〔課題を解決するための手段〕[Means to solve the problem]

本発明は、スクライブ部分の、配線及びＰＡＤ電極自体
のエツチングと同時にその内部にもパターニングする事
を特徴とする。The present invention is characterized in that at the same time as etching the wiring and the PAD electrode itself in the scribe portion, the inside thereof is also patterned.

〔実　施　例〕〔Example〕

以下、本発明について、実施例に基づき説明する。 Hereinafter, the present invention will be explained based on examples.

第１図は半導体基板のスクライブ部分に形成された本発
明の構造を使用したＰＡＤ電極の一実施例である。まず
半導体素子が形成されると同時にモニター用半導体素子
が形成される。FIG. 1 shows an example of a PAD electrode using the structure of the present invention formed on a scribe portion of a semiconductor substrate. First, a semiconductor element is formed and at the same time a semiconductor element for monitoring is formed.

次いで前記モニター用半導体素子の特性を確認するため
に形成されるＡＬ配線及びＰＡＤ電極は、第１図に示し
たように、ダイシング方向に平行なＡＬのない部分がで
きるようなパターンを含めた形で同時に形成する。Next, the AL wiring and PAD electrode that are formed to confirm the characteristics of the monitoring semiconductor element are formed in a shape that includes a pattern that has no AL part parallel to the dicing direction, as shown in FIG. formed at the same time.

次いで前記ＰＡＤ電極を使用して特性が良好と確認され
た後、ダイシング工程に流動される。Next, after it is confirmed that the PAD electrode has good characteristics using the PAD electrode, it is subjected to a dicing process.

次いで前記ダイシング工程を終了し、外部１！極とチッ
プ内ボンディングＰＡＤがボンディングワイヤで結線さ
れた時、第２図に示す様にスクライブＰＡＤのパリがボ
ンディングワイヤに接触する事無く、実装工程を終了す
る。Next, the dicing process is completed, and the external 1! When the pole and the in-chip bonding PAD are connected with the bonding wire, the mounting process is completed without the pole of the scribe PAD coming into contact with the bonding wire, as shown in FIG.

〔発明の効果〕〔Effect of the invention〕

上述の如く、ダイシング工程によって生じた、。 As mentioned above, caused by the dicing process.

スクライブ部分のＰＡＤ電極片であるパリが小さくなる
事により、実装工程に於けるベンディングワイヤとの接
触が防止出来、ボンディング不良が低減される。又金属
をダイシングする事により寿命が短くなるダイシングソ
ーの耐久性も向上される事になる。By reducing the size of the PAD electrode piece at the scribe portion, contact with the bending wire during the mounting process can be prevented, reducing bonding defects. Additionally, the durability of the dicing saw, which has a shortened lifespan due to dicing metal, will also be improved.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の半導体装置の配線及びＰＡＤ電極構造
の一実施例を示す図である。 第２図は本発明の半導体装置の配線又はＰＡＤ電極をダ
イシングした後、実装工程におけるボンディングを終了
した一実施例を示す図である。 １・・・スクライブ領域内ＰＡＤ電極 ２・・・電極材料のない部分 ３・・・チップ内ボンディングＰＡＤ電極４・・・ボン
ディングワイヤ ５・・・ダイシング後のスクライブ領域内ＰＡＤのパリFIG. 1 is a diagram showing one embodiment of the wiring and PAD electrode structure of a semiconductor device of the present invention. FIG. 2 is a diagram showing an embodiment in which bonding in the mounting process is completed after dicing the wiring or PAD electrode of the semiconductor device of the present invention. 1... PAD electrode in the scribe area 2... Portion without electrode material 3... In-chip bonding PAD electrode 4... Bonding wire 5... Paris of the PAD in the scribe area after dicing

Claims (1)

【特許請求の範囲】[Claims] 　半導体基板の一主表面にいくつかのモニター用半導体
素子が形成され、これら素子の電極から出された配線及
びＰＡＤ電極が、上記主表面のスクライブ部分に設けら
れた半導体装置であって、上記配線及びＰＡＤ電極自体
のエッチングと同時にその内部にもパターンを形成した
事を特徴とする半導体装置。A semiconductor device in which several monitoring semiconductor elements are formed on one main surface of a semiconductor substrate, and wiring and PAD electrodes extending from the electrodes of these elements are provided in a scribe portion of the main surface, and the wiring and a semiconductor device characterized in that a pattern is formed inside the PAD electrode at the same time as the etching of the PAD electrode itself.
JP591888A 1988-01-14 1988-01-14 Semiconductor device and manufacturing method Expired - Lifetime JP2867138B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP591888A JP2867138B2 (en) 1988-01-14 1988-01-14 Semiconductor device and manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP591888A JP2867138B2 (en) 1988-01-14 1988-01-14 Semiconductor device and manufacturing method

Publications (2)

Publication Number Publication Date
JPH01186652A true JPH01186652A (en) 1989-07-26
JP2867138B2 JP2867138B2 (en) 1999-03-08

Family

ID=11624273

Family Applications (1)

Application Number Title Priority Date Filing Date
JP591888A Expired - Lifetime JP2867138B2 (en) 1988-01-14 1988-01-14 Semiconductor device and manufacturing method

Country Status (1)

Country Link
JP (1) JP2867138B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03139862A (en) * 1989-10-25 1991-06-14 Fujitsu Ltd Semiconductor device
JP2015046455A (en) * 2013-08-28 2015-03-12 三菱電機株式会社 Semiconductor wafer and method of manufacturing the same

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63115222U (en) * 1987-01-21 1988-07-25

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63115222U (en) * 1987-01-21 1988-07-25

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03139862A (en) * 1989-10-25 1991-06-14 Fujitsu Ltd Semiconductor device
JP2015046455A (en) * 2013-08-28 2015-03-12 三菱電機株式会社 Semiconductor wafer and method of manufacturing the same

Also Published As

Publication number Publication date
JP2867138B2 (en) 1999-03-08

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